IS66WVD2M16DALL Datasheet, PDF (4/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VDD
VDDQ
VSS
VSSQ
ADQ0~
ADQ15
A16~A20
LB#
UB#
CE#
OE#
WE#
CRE
ADV#
Type
Description
Power Supply Core Power supply (1.7V~1.95V)
Power Supply I/O Power supply (1.7V~1.95V)
Power Supply All VSS supply pins must be connected to Ground
Power Supply All VSSQ supply pins must be connected to Ground
Input / Output Address Input(A0~A15)
Data Input/Output (DQ0~DQ15)
Input
Address Input(A16~A20)
Input
Lower Byte select
Input
Upper Byte select
Input
Chip Enable/Select
Input
Output Enable
Input
Write Enable
Input
Input
Control Register Enable: When CRE is HIGH, READ and WRITE operations
access registers.
Address Valid signal
Signal that a valid address is present on the address bus. Address are
latched on the rising edge of ADV# during asynchronous Read/Write
operations. Addresses are latched on the rising edge of CLK with ADV#
low during synchronous operation.
CLK
Input
Clock
Latches addresses and commands on the first rising CLK edge when
ADV# is active in synchronous mode. CLK must be kept static Low during
asynchronous Read/Write operations.
WAIT
Output
WAIT
Data valid signal during burst Read/Write operation. WAIT is used to
arbitrate collisions between refresh and Read/Write operation. WAIT is
also asserted at the end of a row unless wrapping within the burst length.
WAIT is asserted and should be ignored during asynchronous READ
operation. WAIT is gated by CE# and is high-Z when CE# is high.
Rev. A | May 2012
www.issi.com - [e-mail]
4