IS66WVD2M16DALL Datasheet, PDF (21/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Bus Configuration Register
The BCR defines how the CellularRAM device interacts with the system memory bus.
Table 3 describes the control bits in the BCR. At power-up, the BCR is set to 1D1Fh.
The BCR is accessed using CRE and A[19:18] = 10b, or through the configuration
register software sequence with ADQ[15:0] = 0001h on the third cycle.
Table 3. Bus configuration Register
Bit Number
Definition
Remark
20
Reserved
Must be set to “0”
19 – 18
Register Select
00 = Select RCR
01 = Select DIDR
10 = Select BCR
17 – 16
Reserved
Must be set to “0”
15
Operating mode
0 = Synchronous burst access mode (default)
1 = Asynchronous access mode
14
Initial Latency
0 = Variable (default)
1 = Fixed
13 – 11
Latency Count
000 = 9 clock cycles
001 = reserved
010 = 3 clock cycles
011 = 4 clock cycles (default)
100 = 5 clock cycles
101 = 6 clock cycles
110 = 7 clock cycles
111 = reserved
10
WAIT Polarity
0 = Active LOW : Data valid at WAIT HIGH
1 = Active HIGH : Data valid at WAIT LOW (default)
9
Reserved
Must be set to “0”
8
WAIT Configuration
0 = Asserted during delay
1 = Asserted one data cycle before delay (default)
7–6
Reserved
Must be set to “0”
5–4
Output Impedance
00 = Full drive
01 = ½ Drive (default)
10 = ¼ Drive
11 = Reserved
3
Burst mode
0 = Burst wrap within the burst length
1 = Burst no wrap (default)
001 = 4 words
010 = 8 words
2–0
Burst Length
011 = 16 words
111 = continuous (default)
Notes :
Others = Reserved
1.Burst wrap and length apply to both READ and WRITE operations.
Rev. A | May 2012
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