IS66WVD2M16DALL Datasheet, PDF (30/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

AC Characteristics
IS66WVD2M16DALL
Table15 . Asynchronous READ Cycle Timing Requirements
Symbol
Parameter
t_AA
t_AADV
t_AVH
t_AVS
t_BA
t_BHZ
t_CPH
t_CO
t_CVP
t_HZ
t_OE
t_OEW
t_OHZ
t_OLZ
t_VP
t_WZ
Address Acess Time
ADV# Access Time
Address hold from ADV# HIGH
Address setup to ADV# HIGH
UB#, LB# Access Time
UB#, LB# Disable to High-Z Output
CE# HIGH between Subsequent Asynchronous cycles
Chip Select Access Time
CE# low to ADV# HIGH
Chip Disable to High-Z Output
OE# low to Valid Output
OE# low to WAIT Valid
OE# high to High-Z Output
OE# low to Low-Z output
ADV# Low pulse width
CE# high to WAIT High-Z
-70
Unit
Min Max
70
ns
70
ns
2
ns
5
ns
70
ns
7
5
ns
70
ns
7
ns
7
20
ns
1
7.5
7
ns
3
ns
7
ns
7
ns
Notes:
1. Low-Z to High-Z timings are tested with the circuit shown in Figure 23. The High-Z timings
measure a 100mV transition from either VOH or VOL toward VDDQ/2.
2. High-Z to Low-Z timings are tested with the circuit shown in Figure 23. The Low-Z timings
measure a 100mV transition away from the High-Z (VDDQ/2) level toward either VOH or VOL.
Notes
1
1
1
2
1
Rev. A | May 2012
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