IS66WVD2M16DALL Datasheet, PDF (18/52 Pages) Integrated Silicon Solution, Inc – Single device supports asynchronous and burst operation

IS66WVD2M16DALL
Figure 9: Configuration Register READ
– Synchronous Mode Followed by Data READ
CLK
t_CLK
t_ABA
Address
Select
Control
Register
t_SP t_HD
ADQ0-
ADQ15
ADV#
Don’t
Care
t_AS
t_AS
t_CSP
t_ABA
CE#
UB#/LB#
WE#
t_SP ^tHD
OE#
t_KW
HiZ
WAIT
t_HD
CRE⁴
VALID
ADDRESS
t_ACLK t_KOH t_SP t_HD
CR
valid
VALID
ADDRESS
t_ACLK t_KOH
VALID VALID VALID VALID
OUTPUTOUTPUTOUTPUTOUTPUT
t_CBPH3
t_CEM
t_HD
t_OE
t_KW
t_KW
t_KW
t_OHZ
t_WZ
t_SP
Notes:
1. Non-default BCR settings for configuration register READ in synchronous mode, followed by READ ARRAY
operation: Latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. A[19:18] = 00b to load RCR ADQ[15:0]; 10b to load BCR ADQ[15:0]; 01b to load DIDR ADQ[15:0].
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored additional WAIT
cycles caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
4. CRE must be HIGH to access registers.
Rev. A | May 2012
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