IS66WVC1M16ALL Datasheet, PDF (50/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC1M16ALL
IS67WVC1M16ALL
Figure 35: Four-Word Burst WRITE Operation – Variable Latency
t_CLK
CLK
Address
DQ0-
DQ15
NOTE3
ADV#
CE#
VALID
ADDRESS
t_SP
t_HD
t_AS
t_AS
t_CSP
UB#/LB#
WE#
t_SP
t_HD
t_SP
t_HD
DATA IN
DATA IN
DATA IN
DATA IN
t_CEM
t_SP t_HD
t_HD
t_CBPH
t_HD
WAIT ^HiZ
t_CEW
NOTE2
t_KHTL
Write Burst Identified (WE#=LOW)
Notes:
1. Non-default BCR settings for burst WRITE operation, with fixed-length burst of 4, burst wrap enabled:
Variable latency; latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS required if tCSP > 20ns.
Rev.A | October 2013
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