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IS66WVC1M16ALL Datasheet, PDF (43/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation
IS66WVC1M16ALL
IS67WVC1M16ALL
Figure 28: Four-Word Burst READ Operation – Fixed Latency
CLK
Address
DQ0-
DQ15
ADV#
CE#
UB#/LB#
WE#
tAA
VALID
ADDRESS
tSP
tAVH
tSP tHD
tCSP
tAADV
tCO
tSP
tSP tHD
OE#
tCEW
WAIT HiZ
tKOH
VALID
OUTPUT
VALID
OUTPUT
tCEM
tOLZ
tBOE
tKHTL
tCLK
VALID
OUTPUT
VALID
OUTPUT
tHZ
tHD tCBPH
tHD
tHZ
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default fixed latency BCR settings for 4-word burst READ operation: Fixed latency;
latency code two (three clocks); WAIT active LOW; WAIT asserted during delay.
Rev.A | October 2013
www.issi.com – SRAM@issi.com
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