IS66WVC1M16ALL Datasheet, PDF (4/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC1M16ALL
IS67WVC1M16ALL
Signal Descriptions
All signals for the device are listed below in Table 1.
Table 1. Signal Descriptions
Symbol
VDD
VDDQ
VSS
VSSQ
DQ0~DQ15
A0~A19
LB#
UB#
CE#
OE#
WE#
CRE
ADV#
CLK
WAIT
Type
Power Supply
Power Supply
Power Supply
Power Supply
Input / Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Description
Core Power supply (1.7V~1.95V)
I/O Power supply (1.7V~1.95V)
All VSS supply pins must be connected to Ground
All VSSQ supply pins must be connected to Ground
Data Inputs/Outputs (DQ0~DQ15)
Address Input(A0~A19)
Lower Byte select
Upper Byte select
Chip Enable/Select
Output Enable
Write Enable
Control Register Enable: When CRE is HIGH, READ and WRITE operations
access registers.
Address Valid signal
Indicates that a valid address is present on the address inputs. Address
can be latched on the rising edge of ADV# during asynchronous Read and
Write operations. ADV# can be held LOW during asynchronous Read and
Write operations.
Clock
Latches addresses and commands on the first rising CLK edge when
ADV# is active in synchronous mode. CLK must be kept static Low during
asynchronous Read/Write operations and Page Read access operations.
WAIT
Data valid signal during burst Read/Write operation. WAIT is used to
arbitrate collisions between refresh and Read/Write operation. WAIT is
also asserted at the end of a row unless wrapping within the burst length.
WAIT is asserted and should be ignored during asynchronous and page
mode operation. WAIT is gated by CE# and is high-Z when CE# is high.
Rev.A | October 2013
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