IS66WVC1M16ALL Datasheet, PDF (41/67 Pages) Integrated Silicon Solution, Inc – Mixed Mode supports asynchronous write and synchronous read operation

IS66WVC1M16ALL
IS67WVC1M16ALL
Figure 26: Four-Word Burst READ Operation – Variable Latency with refresh collision
t_CLK
CLK
Address
DQ0-
DQ15
ADV#
CE#
UB#/LB#
WE#
VALID
ADDRESS
t_SP
t_HD
t_SP
t_HD
t_CSP
t_SP
t_SP t_HD
OE#
t_CEW
WAIT ^HiZ
t_ACLK
t_KOH
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
VALID
OUTPUT
t_CEM
t_HZ
t_HD t_CBPH
t_OLZ
t_BOE
t_KHTL
t_HD
t_HZ
Read Burst Identified (WE#=HIGH)
Notes:
1. Non-default variable latency BCR settings for 4-word burst READ operation: Latency code
two (three clocks); WAIT active LOW; WAIT asserted during delay.
2. If refresh collision happened, WAIT will be asserted between the latency count number of clock cycles
and 2x the latency count
Rev.A | October 2013
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