ISL12022 Datasheet, PDF (9/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

ISL12022
• Interrupt Mode. The pin provides an interrupt signal
output. This signal notifies a host processor that an alarm
has occurred and requests action. It is an active low
output.
• Frequency Output Mode. The pin outputs a clock signal,
which is related to the crystal frequency. The frequency is
user selectable and enabled via the I²C bus.
Serial Clock (SCL)
The SCL input is used to clock all serial data into and out of
the device. The input buffer on this pin is always active (not
gated). It is disabled when the backup power supply on the
V_BAT pin is activated to minimize power consumption.
Serial Data (SDA)
SDA is a bi-directional pin used to transfer data into and out
of the device. It has an open drain output and may be ORed
with other open drain or open collector outputs. The input
buffer is always active (not gated) in normal mode.
An open drain output requires the use of a pull-up resistor.
The output circuitry controls the fall time of the output signal
with the use of a slope controlled pull-down. The circuit is
designed for 400kHz I²C interface speeds. It is disabled
when the backup power supply on the V_BAT pin is activated.
V_DD, GND
Chip power supply and ground pins. The device will operate
with a power supply from V_DD = 2.7V to 5.5VDC. A 0.1µF
capacitor is recommended on the V_DD pin to ground.
Functional Description
Power Control Operation
The power control circuit accepts a V_DD and a V_BAT input.
Many types of batteries can be used with Intersil RTC
products. For example, 3.0V or 3.6V Lithium batteries are
appropriate, and battery sizes are available that can power
the ISL12022 for up to 10 years. Another option is to use a
super capacitor for applications where V_DD is interrupted for
up to a month. See the “Application Section” on page 25 for
more information.
Normal Mode (V_DD) to Battery-Backup Mode
(V_BAT)
To transition from the V_DD to V_BAT mode, both of the
following conditions must be met:
Condition 1:
V_DD < V_BAT - V_BATHYS
where V_BATHYS ≈ 50mV
Condition 2:
V_DD < V_TRIP
where V_TRIP ≈ 2.2V
Battery-Backup Mode (V_BAT) to Normal Mode
(V_DD)
The ISL12022 device will switch from the V_BAT to V_DD mode
when one of the following conditions occurs:
Condition 1:
V_DD > V_BAT + V_BATHYS
where V_BATHYS ≈ 50mV
Condition 2:
V_DD > V_TRIP + V_TRIPHYS
where V_TRIPHYS ≈ 30mV
These power control situations are illustrated in Figures 11
and 12.
V_DD
V_TRIP
V_BAT
V_BAT - V_BATHYS
BATTERY-BACKUP
MODE
2.2V
1.8V
V_BAT + V_BATHYS
FIGURE 11. BATTERY SWITCHOVER WHEN V_BAT < V_TRIP
V_DD
V_BAT
V_TRIP
V_TRIP
BATTERY-BACKUP
MODE
3.0V
2.2V
V_TRIP + V_TRIPHYS
FIGURE 12. BATTERY SWITCHOVER WHEN V_BAT > V_TRIP
The I²C bus is deactivated in battery-backup mode to reduce
power consumption. Aside from this, all RTC functions are
operational during battery-backup mode. Except for SCL and
SDA, all the inputs and outputs of the ISL12022 are active
during battery-backup mode unless disabled via the control
register.
The device Time Stamps the switchover from V_DD to V_BAT
and V_BAT to V_DD, and the time is stored in t_SV2B and t_SB2V
registers respectively. If multiple V_DD power-down sequences
occur before status is read, the earliest V_DD to V_BAT
power-down time is stored and the most recent V_BAT to V_DD
time is stored.
Temperature conversion and compensation can be enabled
in battery-backup mode. Bit BTSE in the BETA register
controls this operation, as described in “BETA Register
(BETA)” on page 17.
9
FN6659.2
June 23, 2009