ISL12022 Datasheet, PDF(20/28 Page) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

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ISL12022 Datasheet, PDF (20/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

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ISL12022

Once the registers are set, the following waveform will be

seen at IRQ/FOUT:

RTC AND ALARM REGISTERS ARE BOTH â30sâ

DST Control Registers (DSTCR)

8 bytes of control registers have been assigned for the

Daylight Savings Time (DST) functions. DST beginning (set

Forward) time is controlled by the registers DstMoFd,

DstDwFd, DstDtFd, and DstHrFd. DST ending time (set

Backward or Reverse) is controlled by DstMoRv, DstDwRv,

DstDtRv and DstHrRv.

60s

FIGURE 13. IRQ/FOUT WAVEFORM

Note that the status register ALM bit will be set each time the

alarm is triggered, but does not need to be read or cleared.

Time Stamp VDD to Battery Registers (TSV2B)

The TSV2B Register bytes are identical to the RTC register

bytes, except they do not extend beyond the Month. The Time

Stamp captures the FIRST VDD to Battery Voltage transition

time, and will not update upon subsequent events, until cleared

(only the first event is captured before clearing). Set CLRTS = 1

to clear this register (Add 09h, PWR_VDD register).

Note that the time stamp registers are cleared to all â0â,

including the month and day, which is different from the RTC

and alarm registers (those registers default to 01h). This is

the indicator that no time stamping has occurred since the

last clear or initial power-up. Once a time stamp occurs,

there will be a non-zero time stamp.

Tables 20 and 21 describe the structure and functions of the

DSTCR.

DST FORWARD REGISTERS (20H TO 23H)

DST forward is controlled by the following DST Registers:

DST Enable

DSTE is the DST Enabling Bit located in Bit 7 of register 20h

(DstMoFdxx). Set DSTE = 1 will enable the DSTE function.

Upon powering up for the first time (including battery), the

DSTE bit defaults to â0â. When DSTE is set to â1â the RTC

time must be at least one hour before the scheduled DST

time change for the correction to take place. When DSTE is

set to â0â, the DSTADJ bit in the Status Register

automatically resets to â0â.

DST Month Forward

DstMoFd sets the Month that DST starts. The format is the

same as for the RTC register month, from 1 to 12. The

default value for the DST begin month is 00h.

Time Stamp Battery to VDD Registers (TSB2V)

The Time Stamp Battery to VDD Register bytes are identical

to the RTC register bytes, except they do not extend beyond

Month. The Time Stamp captures the LAST transition of

VBAT to VD (only the last event of a series of power-up/down

events is retained). Set CLRTS = 1 to clear this register (Add

09h, PWR_VDD register).

TABLE 20. DST FORWARD REGISTERS

ADDRESS FUNCTION

20h

Month Forward DSTE

MoFd20

MoFd13

21h

Day Forward

DwFdE

WkFd12

WkFd11

WkFd10

22h

Date Forward

DtFd21

DtFd20

DtFd13

23h

Hour Forward

HrFd21

HrFd20

HrFd13

MoFd12

DwFd12

DtFd12

HrFd12

MoFd11

DwFd11

DtFd11

HrFd11

MoFd10

DwFd10

DtFd10

HrFd10

ADDRESS

NAME

24h

Month Reverse

25h

Day Reverse

26h

Date Reverse

27h

Hour Reverse

TABLE 21. DST REVERSE REGISTERS

MoRv20 MoRv13

DwRvE

WkRv12 WkRv11 WkRv10

DtRv21

DtRv20

DtRv13

HrRv21

HrRv20

HrRv13

MoRv12

DwRv12

DtRv12

HrRv12

MoRv11

DwRv11

DtRv11

HrRv11

MoRv10

DwRv10

DtRv10

HrRv10

FN6659.2

June 23, 2009

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