ISL12022 Datasheet, PDF (11/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

ISL12022
the crystal. Initial values are preset and recalled on initial
power-up for the Initial AT and DT settings (IATR, IDTR),
temperature coefficient (ALPHA), crystal capacitance
(BETA), and the crystal turn-over temperature (XTO). These
initial values are typical of units available on the market,
although the user may program specific values after testing
for best accuracy. The function can be enabled/disabled at
any time and can be used in battery mode as well.
Register Descriptions
The battery-backed registers are accessible following a
slave byte of “1101111x” and reads or writes to addresses
[00h:2Fh]. The defined addresses and default values are
described in the Table 1. The battery backed general
purpose SRAM has a different slave address (1010111x), so
it is not possible to read/write that section of memory while
accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing
a byte or a page write operation directly to any register
address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (9 bytes): Address 07h to 0Fh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to
1Ah.
5. Time Stamp for V_DD Status (5 bytes): Address 1Bh to
1Fh.
6. Daylight Savings Time (8 bytes): 20h to 27h.
7. TEMP (2 bytes): 28h to 29h
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte):
2Dh
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to
06h) only when the WRTC bit (bit 6 of address 08h) is set to
“1”. A multi-byte read or write operation should be limited to
one section per operation for best RTC time keeping
performance.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a
sequential read. For the RTC and Alarm registers, the read
instruction latches all clock registers into a buffer, so an
update of the clock does not change the time being read. At
the end of a read, the master supplies a stop condition to
end the operation and free the bus. After a read, the address
remains at the previous address +1 so the user can execute
a current address read and continue reading the next
register. When the previous address is 2Fh, the next
address will wrap around to 00h.
It is not necessary to set the WRTC bit prior to writing into
the control and status, alarm, and user SRAM registers.
REG
ADDR. SECTION NAME
00h
SC
01h
MN
02h
HR
03h
RTC
DT
04h
MO
05h
YR
06h
DW
07h
SR
08h
INT
09h
PWR_VDD
0Ah
PWR_VBAT
0Bh
CSR
ITRO
0Ch
ALPHA
0Dh
BETA
0Eh
FATR
0Fh
FDTR
7
0
0
MIL
0
0
YR23
0
BUSY
ARST
CLRTS
IDTR01
D
TSE
0
0
TABLE 1. REGISTER MEMORY MAP
BIT
6
5
4
3
2
SC22
SC21
SC20
SC13
SC12
MN22
MN21
MN20
MN13
MN12
0
HR21
HR20
HR13
HR12
0
DT21
DT20
DT13
DT12
0
0
MO20
MO13
MO12
YR22
YR21
YR20
YR13
YR12
0
0
0
0
DW2
OSCF DSTADJ
ALM
LVDD
LBAT85
WRTC
IM
FOBATB
FO3
FO2
D
RESEALB
D
VB85Tp2
D
VB85Tp1
D
VB85Tp0
V_DDTrip2
VB75Tp2
IDTR00 IATR05 IATR04 IATR03 IATR02
ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2
BTSE
BTSR
BETA4
BETA3
BETA2
0
FFATR5 FATR4
FATR3
FATR2
0
0
FDTR4 FDTR3 FDTR2
1
SC11
MN11
HR11
DT11
MO11
YR11
DW1
LBAT75
FO1
V_DDTrip1
VB75Tp1
IATR01
ALPHA1
BETA1
FATR1
FDTR1
0
SC10
MN10
HR10
DT10
MO10
YR10
DW0
RTCF
FO0
V_DDTrip0
VB75Tp0
IATR00
ALPHA0
BETA0
FATR0
FDTR0
RANGE DEFAULT
0 to 59
00h
0 to 59
00h
0 to 23
00h
1 to 31
01h
1 to 12
01h
0 to 99
00h
0 to 6
00h
N/A
01h
N/A
01h
N/A
00h
N/A
00h
N/A
20h
N/A
46h
N/A
00h
N/A
00h
N/A
00h
11
FN6659.2
June 23, 2009