ISL12022 Datasheet, PDF (26/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

ISL12022
compensate for temperature variation. A typical 32.768kHz
crystal used with RTC devices has a temperature versus
frequency curve, as shown in Figure 21.
0
-20
-40
-60
-80
-100
-120
-140
-160
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
FIGURE 21. RTC CRYSTAL TEMPERATURE DRIFT
The curve in Figure 21 follows Equation 7:
Δf = α • (T – T₀ )²
(EQ. 7)
Where α is the temperature constant, with a typical value of
0.034 ppm/°C.
T₀ is the turnover temperature of the crystal, which is the
apex of the parabolic curve. If the two factors α and T₀ are
known, it is possible to correct for crystal temperature error
to very high accuracy.
The crystal will have an initial accuracy error at room
temperature, typically specified at ±20°C. The other
important characteristic is the capacitances associated with
the crystal. The load capacitance is normally specified at
12.5pF, although it can be lower in some cases. There is
also a motional capacitance which affects the ability of the
load capacitance to pull the oscillation frequency, and it is
usually in the range of 2.2fF to 4.0fF.
RTC CLOCK CONTROL
The ISL12022 uses two mechanisms to adjust the RTC
clock and correct for the temperature error of the external
crystal.
The Analog Trimming (AT) adjusts the load capacitance
seen by the crystal. Analog switches connect the appropriate
capacitance to change the frequency in increments of 1ppm.
The adjustment range for the ISL12022 is +32/-31ppm.
The AT can be further refined using the BETA register. the
BETA register function is to allow for changes in C_M
(motional capacitance) which will affect the incremental
frequency change of the AT adjustment. A simple test
procedure uses the BETA register to bring the step size back
to 1ppm.
Normally, the crystal frequency is adjusted at room
temperature to zero out the frequency error using the IATRxx
register bits (initial Analog Trimming). In addition, the IATRxx
setting is varied up and down to record the variation in
oscillator frequency compared to the step change in IATRxx.
Once that value is known then the BETA register is used to
adjust the step size to be as close to 1ppm per IATRxx step
as possible. After that adjustment is made, then any
ISL12022 temperature compensation adjustments will use a
1ppm change for each bit change in the internal AT
adjustment.
The Digital Trimming (DT) uses clock pulse add/subtract
logic to change the RTC timing during temperature
compensation. The DT steps are much coarser than the AT
steps and are therefore used for large adjustments. The DT
steps are 30.5ppm, and the range is from -305ppm to
+305ppm. The Frequency Output function will show the
clock variation with DT settings, except for the 32,768Hz
setting which only shows the AT control.
ACTIVE TEMPERATURE COMPENSATION
The ISL12022 contains an intelligent logic circuit which takes
the temperature sensor digital value as the only input
variable. It then uses the register values for the crystal
variables α and T₀, and combines those with calibration from
the BETA and ITR0 registers to produce “Final” values for
the AT and DT, known as FATR (Final AT Register) and
FDTR (Final DT Register). Those AT and DT values
combine to directly compensate for the temperature error
shown in Figure 21.
The temperature sensor produces a new value every 60s (or
up to 10 minutes in battery mode), which triggers the logic to
calculate a new AT/DT value set. For every temperature
calculation result, there can only be one corresponding
AT/DT correction value.
SIGNALS
FROM THE
MASTER
S
T _{IDENTIFICATION}
A
BYTE WITH
R
R/W = 0
T
ADDRESS
BYTE
S
T _{IDENTIFICATION}
A _{BYTE WITH}
R
R/W = 1
T
S
A
A
T
C
C
O
K
K
P
SIGNAL AT
SDA
11011110
A
SIGNALS FROM
C
THE SLAVE
K
11011111
A
A
C
C _{FIRST READ}
K
K _{DATA BYTE}
FIGURE 20. READ SEQUENCE (CSR SLAVE ADDRESS SHOWN)
LAST READ
DATA BYTE
26
FN6659.2
June 23, 2009