ISL12022 Datasheet, PDF (16/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

ISL12022
TABLE 9. BATTERY LEVEL MONITOR TRIP BITS
(VB75TP<2:0>)
VB75Tp2
VB75Tp1
VB75Tp0
BATTERY
ALARM TRIP
LEVEL
(V)
0
0
0
1.875
0
0
1
2.025
0
1
0
2.250
0
1
1
2.475
1
0
0
2.700
1
0
1
3.750
1
1
0
4.125
Initial AT and DT setting Register (ITRO)
These bits are used to trim the initial error (at room
temperature) of the crystal. Both Digital Trimming (DT) and
Analog Trimming (AT) methods are available. The digital
trimming uses clock pulse skipping and insertion for
frequency adjustment. Analog trimming uses load
capacitance adjustment to pull the oscillator frequency. A
range of +62.5ppm to -61.5ppm is possible with combined
digital and analog trimming.
AGING AND INITIAL TRIM DIGITAL TRIMMING BITS
(IDTR0<1:0>)
These bits allow ±30.5ppm initial trimming range for the
crystal frequency. This is meant to be a coarse adjustment if
the range needed is outside that of the IATR control.
See Table 10. The IDTR0 register should only be changed
while the TSE (Temp Sense Enable) bit is “0”.
TABLE 10. IDTR0 TRIMMING RANGE
IDTR01
IDTR00
TRIMMING RANGE
0
0
Default/Disabled
0
1
+30.5ppm
1
0
0ppm
1
1
-30.5ppm
AGING AND INITIAL ANALOG TRIMMING BITS
(IATR0 <5:0>)
The analog trimming register allows +32ppm to -31ppm
adjustment in 1ppm/bit increments. This enables fine
frequency adjustment for trimming initial crystal accuracy error
or to correct for aging drift. The IATR0 register should only be
changed while the TSE (Temp Sense Enable) bit is “0”.
TABLE 11. INITIAL AT AND DT SETTING REGISTER
ADDR 7
6
5
4
3
2
1
0
0Bh IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
Aging adjustment is normally a few ppm and can be handled
by writing to the IATR section.
TABLE 12. IATR0 TRIMMING RANGE
TRIMMING
IATR05 IATR04 IATR03 IATR02 IATR01 IATR00 RANGE
0
0
0
0
0
0
+32
0
0
0
0
0
1
+31
0
0
0
0
1
0
+30
0
0
0
0
1
1
+29
0
0
0
1
0
0
+28
0
0
0
1
0
1
+27
0
0
0
1
1
0
+26
0
0
0
1
1
1
+25
0
0
1
0
0
0
+24
0
0
1
0
0
1
+23
0
0
1
0
1
0
+22
0
0
1
0
1
1
+21
0
0
1
1
0
0
+20
0
0
1
1
0
1
+19
0
0
1
1
1
0
+18
0
0
1
1
1
1
+17
0
1
0
0
0
0
+16
0
1
0
0
0
1
+15
0
1
0
0
1
0
+14
0
1
0
0
1
1
+13
0
1
0
1
0
0
+12
0
1
0
1
0
1
+11
0
1
0
1
1
0
+10
0
1
0
1
1
1
+9
0
1
1
0
0
0
+8
0
1
1
0
0
1
+7
0
1
1
0
1
0
+6
0
1
1
0
1
1
+5
0
1
1
1
0
0
+4
0
1
1
1
0
1
+3
0
1
1
1
1
0
+2
0
1
1
1
1
1
+1
1
0
0
0
0
0
0
1
0
0
0
0
1
-1
1
0
0
0
1
0
-2
1
0
0
0
1
1
-3
1
0
0
1
0
0
-4
1
0
0
1
0
1
-5
1
0
0
1
1
0
-6
1
0
0
1
1
1
-7
1
0
1
0
0
0
-8
1
0
1
0
0
1
-9
1
0
1
0
1
0
-10
1
0
1
0
1
1
-11
1
0
1
1
0
0
-12
1
0
1
1
0
1
-13
1
0
1
1
1
0
-14
1
0
1
1
1
1
-15
1
1
0
0
0
0
-16
1
1
0
0
0
1
-17
16
FN6659.2
June 23, 2009