ISL12022 Datasheet, PDF (24/28 Pages) Intersil Corporation – Real Time Clock with On Chip ±5ppm Temp Compensation

ISL12022
SIGNALS FROM
THE MASTER
WRITE
S
T
A ^{IDENTIFICATION}
R
BYTE
T
ADDRESS
BYTE
S
DATA
T
BYTE
O
P
SIGNAL AT SDA
11011110 0000
SIGNALS FROM
THE ISL12022
A
A
A
C
C
C
K
K
K
FIGURE 16. BYTE WRITE SEQUENCE (SLAVE ADDRESS FOR CSR SHOWN)
The ISL12022 responds with an ACK after recognition of a
START condition followed by a valid Identification Byte, and
once again, after successful receipt of an Address Byte. The
ISL12022 also responds with an ACK after receiving a Data
Byte of a write operation. The master must respond with an
ACK after receiving a Data Byte of a read operation.
Device Addressing
Following a start condition, the master must output a Slave
Address Byte. The 7 MSBs are the device identifiers. These
bits are “1101111” for the RTC registers and “1010111” for the
User SRAM.
The last bit of the Slave Address Byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 17).
After loading the entire Slave Address Byte from the SDA bus,
the ISL12022 compares the device identifier and device select
bits with “1101111” or “1010111”. Upon a correct compare, the
device outputs an acknowledge on the SDA line.
Following the Slave Byte is a one byte word address. The word
address is either supplied by the master device or obtained
from an internal counter. On power-up, the internal address
counter is set to address 00h, so a current address read starts
at address 00h. When required, as part of a random read, the
master must supply the 1 Word Address Bytes, as shown in
Figure 20.
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the Control/Status Registers, the slave byte
must be “1101111x” in both places.
1
1
0
1
11
1
R/W
SLAVE
ADDRESS BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL12022 responds with an ACK. At this time, the I²C
interface enters a standby state.
Read Operation
A Read operation consists of a three byte instruction, followed
by one or more Data Bytes (see Figure 20). The master initiates
the operation issuing the following sequence: a START, the
Identification byte with the R/W bit set to “0”, an Address Byte, a
second START, and a second Identification byte with the R/W
bit set to “1”. After each of the three bytes, the ISL12022
responds with an ACK. Then the ISL12022 transmits Data
Bytes as long as the master responds with an ACK during the
SCL cycle following the eighth bit of each byte. The master
terminates the read operation (issuing a STOP condition)
following the last bit of the last Data Byte (see Figure 20).
The Data Bytes are from the memory location indicated by
an internal pointer. This pointer’s initial value is determined
by the Address Byte in the Read operation instruction, and
increments by one during transmission of each Data Byte.
After reaching the memory location 2Fh, the pointer “rolls
over” to 00h, and the device continues to output data for
each ACK received.
TABLE 26. SUGGESTED SURFACE MOUNT CRYSTALS
MANUFACTURER
PART NUMBER
Citizen
CM200S
Epson
MC-405, MC-406
Raltron
RSM-200S
SaRonix
32S12
Ecliptek
ECPSM29T-32.768K
ECS
ECX-306
Fox
FSM-327
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 17. SLAVE ADDRESS, WORD ADDRESS, AND DATA
BYTES
24
FN6659.2
June 23, 2009