X5043S8ZT1 Datasheet, PDF (8/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
V_TRIP Programming
Execute
Reset V_TRIP
Sequence
Set V_CC = V_CC Applied =
Desired V_TRIP
New V_CC Applied
=
Old V_CC Applied
- Error
Execute
Set V_TRIP
Sequence
New V_CC Applied
=
Old V_CC Applied
- Error
Apply 5V to V_CC
Decrement V_CC
(V_CC = V_CC–10mV)
Execute
Reset V_TRIP
Sequence
NO
Error ≤ -Emax
RESET pin
goes active?
YES
Measured V_TRIP
-Desired V_TRIP
Error ≥ Emax
-Emax < Error < Emax
DONE
SPI Serial Memory
The memory portion of the device is a CMOS Serial
EEPROM array with Intersil’s block lock protection. The array
is internally organized as 512 x 8 bits. The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Intersil’s proprietary Direct Write^™ cell,
providing a minimum endurance of 1,000,000 cycles and a
minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device contains an 8-bit instruction register that controls
the operation of the device. The instruction code is written to
the device via the SI input. There are two write operations
that requires only the instruction byte. There are two read
operations that use the instruction byte to initiate the output
of data. The remainder of the operations require an
instruction byte, an 8-bit address, then data bytes. All
instruction, address and data bits are clocked by the SCK
input. All instructions (Table 1), addresses and data are
transferred MSB first.
Clock and Data Timing
Data input on the SI line is latched on the first rising edge of
SCK after CS goes LOW. Data is output on the SO line by
the falling edge of SCK. SCK is static, allowing the user to
stop the clock and then start it again to resume operations
where left off. CS must be LOW during the entire operation.
Emax = Maximum Desired Error
FIGURE 4. V_TRIP PROGRAMMING SEQUENCE
INSTRUCTION NAME
WREN
WRDI
RSDR
WRSR
READ
WRITE
TABLE 1. INSTRUCTION SET
INSTRUCTION FORMAT*
OPERATION
0000 0110
Set the Write Enable Latch (Enable Write Operations)
0000 0100
Reset the Write Enable Latch (Disable Write Operations)
0000 0101
Read Status Register
0000 0001
Write Status Register (Watchdog and Block Lock)
0000 A₈011
0000 A₈010
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address (1 to 16 bytes)
Note: *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
8
FN8126.2
March 16, 2006