X5043S8ZT1 Datasheet, PDF (12/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10 12 13 14 15 16 17 18 19 20 21 22 23
Instruction
8
8 Bit Address
Data Byte 1
76 5
3 2 107 6 5 43 2 10
9^th Bit of Address
CS
SCK
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Data Byte 2
Data Byte 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data Byte N
654 321 0
FIGURE 9. WRITE MEMORY SEQUENCE
Operational Notes
The device powers-up in the following state:
1. The device is in the low power standby state.
2. A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
3. SO pin is high impedance.
4. The Write Enable Latch is reset.
5. The Flag Bit is reset.
6. Reset Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• Block Protect bits provide additional level of write
protection for the memory array.
• The WP pin LOW blocks nonvolatile write operations.
12
FN8126.2
March 16, 2006