X5043S8ZT1 Datasheet, PDF (10/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
WREN CMD
(WEL)
0
x
1
DEVICE PIN (WP)
x
0
1
TABLE 2. DEVICE PROTECT MATRIX
MEMORY BLOCK
PROTECTED AREA
UNPROTECTED AREA
Protected
Protected
Protected
Protected
Protected
Writable
STATUS REGISTER
(BL0, BL1, WD0, WD1)
Protected
Protected
Writable
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
High Impedance
SO
Data Out
76543210
MSB
FIGURE 6. READ STATUS REGISTER SEQUENCE
CS
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
Data Byte
7 6 5 43 2 1 0
High Impedance
FIGURE 7. WRITE STATUS REGISTER SEQUENCE
10
FN8126.2
March 16, 2006