X5043S8ZT1 Datasheet, PDF (2/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

Typical Application
2.7-5.0V
VCC
X5043
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
X5043, X5045
Block Diagram
V_CC
CS/WDI
SI
SO
SCK
WP
+
- VTRIP
POR and Low
Voltage Reset
Generation
Reset & Watchdog
Timebase
Watchdog
Transition
Detector
Watchdog
Timer
Reset
Command
Decode &
Control
Logic
Protect Logic
Status
Register
EEPROM
Array
4Kbits
RESET (X5043)
RESET (X5045)
X5043, X5045
STANDARD V_TRIP LEVEL
4.63V (+/-2.5%)
SUFFIX
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 3. for
more details
For Custom Settings, call Intersil.
2
FN8126.2
March 16, 2006