X5043S8ZT1 Datasheet, PDF (7/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
WP
CS
SCK
SI
V_P = 15-18V
0 1 23 4 56 7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
8 Bits
06h
WREN
02h
Write
03h
Address
FIGURE 2. RESET V_TRIP LEVEL SEQUENCE (V_CC > 3V. WP = 15–18V)
00h
Data
V_TRIP
Adj.
V_P
Adjust
Run
1
8
2 X5043 7
3 ^X5045 6
4
5
4.7K
RESET
FIGURE 3. SAMPLE V_TRIP RESET CIRCUIT
µC
SCK
SI
SO
CS
7
FN8126.2
March 16, 2006