X5043S8ZT1 Datasheet, PDF (15/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

Serial Output Timing
CS
SCK
SO
X5043, X5045
t_CYC
t_WH
t_V
t_HO
t_WL
MSB Out MSB–1 Out
t_LAG
t_DIS
LSB Out
SI
ADDR
LSB IN
Serial Input Timing
CS
SCK
SI
t_LEAD
t_SU
t_H
MSB In
SO
Symbol Table
High Impedance
WAVEFORM INPUTS
OUTPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
t_CS
t_LAG
t_RI
tFI
LSB In
15
FN8126.2
March 16, 2006