X5043S8ZT1 Datasheet, PDF (14/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
Equivalent A.C. Load Circuit at 5V V_CC
5V
5V
1.64kΩ
4.6kΩ
Output
1.64kΩ
RESET/RESET
30pF
30pF
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
2.7V–5.5V
SYMBOL
PARAMETER
MIN
MAX
DATA INPUT TIMING
f_SCK
t_CYC
t_LEAD
t_LAG
t_WH
t_WL
t_SU
t_H
t_RI(4)
t_FI(4)
t_CS
t_WC(5)
Clock Frequency
Cycle Time
CS Lead Time
CS Lag Time
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
0
3.3
300
150
150
130
130
30
30
2
2
100
10
UNIT
MHz
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ms
Data Output Timing
SYMBOL
f_SCK
t_DIS
t_V
t_HO
t_RO(4)
t_FO(4)
Clock Frequency
Output Disable Time
Output Valid from Clock Low
Output Hold Time
Output Rise Time
Output Fall Time
PARAMETER
2.7–5.5V
MIN
MAX
0
3.3
150
120
0
50
50
UNIT
MHz
ns
ns
ns
ns
ns
NOTES:
4. This parameter is periodically sampled and not 100% tested.
5. t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
14
FN8126.2
March 16, 2006