X5043S8ZT1 Datasheet, PDF (16/21 Pages) Intersil Corporation – CPU Supervisor with 4K SPI EEPROM

X5043, X5045
Power-Up and Power-Down Timing
V_CC
V_TRIP
0 Volts
t_R
RESET (X5043)
t_PURST
t_PURST
RESET (X5045)
V_TRIP
t_F
t_RPD
RESET Output Timing
SYMBOL
PARAMETER
V_TRIP
Reset Trip Point Voltage, (-4.5A)
Reset Trip Point Voltage, (Blank)
Reset Trip Point Voltage, (-2.7A)
Reset Trip Point Voltage, (-2.7)
t_PURST
t_RPD(6)
t_F(6)
t_R(6)
V_RVALID
Power-up Reset Time Out
V_CC Detect to Reset/Output
V_CC Fall Time
V_CC Rise Time
Reset Valid V_CC
NOTE:
6. This parameter is periodically sampled and not 100% tested.
CS/WDI vs. RESET/RESET Timing
CS/WDI
RESET
(5043)
RESET
(5045)
t_CST
t_WDO
t_RST
MIN
TYP
4.5
4.62
4.25
4.38
2.85
2.92
2.55
2.62
100
200
10
0.1
1
t_WDO
t_RST
MAX
4.75
4.5
3.0
2.7
400
500
UNIT
V
ms
ns
µs
ns
V
RESET/RESET Output Timing
SYMBOL
PARAMETER
t_WDO
Watchdog Time Out Period,
WD1 = 1, WD0 = 1 (default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t_CST
CS Pulse Width to Reset the Watchdog
t_RST
Reset Time Out
MIN
TYP
MAX
UNIT
OFF
100
200
300
ms
450
600
800
ms
1
1.4
2
sec
400
ns
100
200
400
ms
16
FN8126.2
March 16, 2006