D2-45057_14 Datasheet, PDF (8/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
SPI™ Master Mode Interface Port Timing T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
t_V
MOSI Valid From Clock Edge
t_S
MISO Setup to Clock Edge
t_H
MISO Hold From Clock Edge
t_WI
nSS Minimum Width
-
8
ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
SPI™ Slave Mode Interface Port Timing T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
t_V
MISO Valid From Clock Edge
t_S
MOSI Setup to Clock Edge
t_H
MOSI Hold From Clock Edge
t_WI
nSS Minimum Width
3 system clocks + 2ns
10
-
ns
1 system clock + 2ns
3 system clocks + 2ns
SCK(CPHA = 1, CPOL = 0)
SCK(CPHA = 0, CPOL = 0)
MOSI
MISO(CPHA = 0)
t_V
t_V
t_H
t_S
t_WI
nSS
FIGURE 3. SPI TIMING
8
FN6785.0
July 29, 2010