D2-45057_14 Datasheet, PDF (19/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Output Options
The D2-45057, D2-45157 devices provide four
configuration options for the power stage outputs. The
power stage configuration is selected by strapping the
OCFG0 and OCFG1 pins high or low. These defined
configurations include:
• 2 Channels of Full Bridge, 4-Quadrant Outputs,
• 2 Channels of Full Bridge, 2-Quadrant Outputs
• 4 Channels of Half-Bridge Outputs
• 2 Channels Half-Bridge, Plus 1 Channel Full Bridge
Audio processing routing and control supporting the
output stage configurations is defined by the logical high
or low strapping of the nERROR/CFG0 and PSSYNC/CFG1
pins. Audio path definition, audio path output routing,
and output stage configurations are automatically set to
one of the four available modes, based on these
configuration settings.
PWM Audio Outputs
Three PWM outputs provide audio for up to three
line-level outputs. Audio processing channel assignment
is mapped to these PWM outputs, based on the device’s
available configuration settings.
Using only a simple passive filter, the PWM outputs will
drive line-level outputs at a nominal 1V_RMS. With
addition of active filter configurations, these can also
drive headphone outputs, or 2V_rms or higher line
outputs. (Alternately, these PWM outputs could also be
used to drive powered outputs, using additional power
stages on the system design.)
Control and Operation
Control Register Summary
The control interface provides access to the registers
used for audio processing blocks and signal flow
parameters. Audio input selection (I²S input or S/PDIF
receiver input) and all programmable data elements used
in the audio processing paths are controlled through
these register parameters, and each parameter is
defined with its specific register address. Programming
details, register identification, and parameter calculations
are provided in the DAE-4/DAE-4P Register API
Specification document.
I²C 2-Wire Control Interface
The D2-45057, D2-45157 device includes a 2-Wire I²C
compatible interface for communicating with an external
controller. This interface is usable through either an
external microcontroller bus, or for communication to
EEPROMs, or other compatible peripheral chips.
The I²C interface supports normal and fast mode
operation and is multi-master capable. In a D2-45057,
D2-45157 system application, it operates as an I²C slave
device, where the system controller operates as the
I²C master.
Reading and Writing Control Registers
All reads or writes to registers (shown in Figures 14 and
15) begin with a Start Condition, followed by the Device
Address byte, three Register Address bytes, three Data
bytes and a Stop Condition.
Register writes through the I²C interface are initiated by
setting the read/write bit that is within the device
address byte. Write sequence shown in Figure 14 is
described in Table 2.
TABLE 2. I²C WRITE SEQUENCE
BYTE
NAME
DESCRIPTION
0 Device Address
Device Address, With R/W
bit set
1 Register Address [23:16] Upper 8 bits of address
2 Register Address [15:8] Middle 8 bits of address
3 Register Address [7:0] Lower 8 bits of address
4 Data[23:16]
Upper 8 bits of write data
5 Data[15:8]
Middle 8 bits of write data
6 Data[7:0]
Lower 8 bits of write data
All reads to registers, shown in Figure 15, require two
steps. First, the master must send a dummy write which
consist of sending a Start, followed by the device address
with the write bit set, and three register address bytes.
Then, the master must send a repeated Start, following
with the device address with the read/write bit set to
read, and then read the next three data bytes. The
master must Acknowledge (ACK) the first two read bytes
and send a Not Acknowledge (NACK) on the third byte
received and a Stop condition to complete the
transaction. The device's control interface acknowledges
each byte by pulling SDA low on the bit immediately
following each write byte. The read sequence shown in
Figure 15 is described in Table 3.
TABLE 3. I²C READ SEQUENCE
BYTE
NAME
DESCRIPTION
0 Device Address
Device Address, With Write
bit set
1 Register Address [23:16] Upper 8 bits of address
2 Register Address [15:8] Middle 8 bits of address
3 Register Address [7:0] Lower 8 bits of address
4 Device Address
5 Data[23:16]
Device Address, With Read
bit set
Upper 8 bits of write data
6 Data[15:8]
Middle 8 bits of write data
7 Data[7:0]
Lower 8 bits of write data
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FN6785.0
July 29, 2010