D2-45057_14 Datasheet, PDF (22/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
completion of reset and when the device firmware begins
operating, this pin becomes the PSSYNC output.
Power Sequence Requirements
Voltage sensors and brownout detectors monitor supply
voltages to the device. The logic and built-in protection of
this voltage monitoring prevents operation until all
supply voltages are within their specified limits. However,
during application of power, the CVDD and RVDD
(including PWMVDD) voltages should be brought up
together to avoid high current transients that could fold
back a power supply regulator.
During application of power to the system and while the
CVDD voltage (nominal +1.8V) is below its minimum
specified limit, the RVDD and PWMVDD supplies (nominal
+3.3V) must not exceed the voltage that is present at
CVDD. (i.e., if V_CVDD < minimum-specified, then
V_RVDD/PWMVDD must be < V_CVDD.) After CVDD has
reached its minimum limit, RVDD/PWMVDD can then
continue to increase to its normal design (3.3V) value.
(PLLVDD may be brought up separately.)
Best practice would be for all supplies to feed from
regulators using a common power source. Typically this
can be achieved by using a single low-voltage supply
power source and regulating the 3.3V and 1.8V supplies
from that source. Also, as noted in the pin specifications
of this document, all voltages of the same names must
be tied together at the board level.
REG5V
The output stage internal drivers require their own
+5VDC supply voltage. An on-chip regulator operates
from the VDDHV voltage to produce this +5V voltage.
The REG5V pin is used for external capacitor connection
to filter this regulated voltage. A 1.0µF and 0.1µF
capacitor should be connected to this pin, and the
connection should be made as close as practical to the
pin. This internal +5V is used only by the output stage
drivers. No other connection is to be made to this pin.
Pin and Control Block Functions
I/O Control Pins
Several device pins are used as specific-function inputs
and outputs to control amplifier and device operation.
These pins are implemented within the device hardware
as general purpose inputs/outputs. However, their
operation is not programmable, and their specific
function is totally defined by the D2-45057, D2-45157
internal firmware. Functions of these pins are defined in
the pin definition list, and additional detail is included
within the descriptions of the functional blocks where
these pins are used.
Some pins are multiple-purpose, where their functions
are defined accordingly by the operational state (e.g.,
reset, initializing, booting, running) of the D2-45057,
D2-45157 device. These multiple-purpose pins and their
descriptions and uses are described in more detail in
Table 5 on page 24.
nPDN Input Pin
The nPDN pin is a control input that is used to
power-down the outputs. When this input is pulled low,
all audio outputs turn off and become inactive, internal
PWM drive to output stages is turned off, and all output
stages float. Internal logic and other references remain
active during this power-down state. Asserting nPDN also
causes all four nERROR[0:3] outputs to pull (active) low.
Each of the four output stages incorporate their own
latching overcurrent hardware shutdown logic, in
addition to the separate protection events that occur
through firmware control from an overcurrent condition.
Firmware protection control will perform other steps to
clear this hardware latched shutdown, although asserting
nPDN will also reset the hardware-latched state.
The nPDN pin is active low, and inactive when at logic
high level. In normal operation, it is held high with
pull-up to the RVDD supply.
nERROR[0-3] Output Pins
Each of the four output stages includes a two-level
overload and overcurrent monitor. An overcurrent or
overload condition asserts the nERROR output for that
channel.
Also, an undervoltage condition for the voltages used by
the output stages (HVDD[A:D]/VDDHV, REG5V,
PWMVDD), or assertion of nPDN, will cause all four
nERROR outputs to assert.
The nERROR pins are open drain, active-low, and can be
wire-or connected together. Depending on the output
mode configuration where more than one output stage
may be used for an audio channel, nERROR pins
associated with that audio channel are connected
together to provide monitoring status.
In applications where multiple power stage outputs are
defined for an audio channel, the nERROR pins for these
power stages would be tied together, and also tied to the
PROTECT input pin associated with that audio channel.
Refer to Table 6 on page 25, that shows these
connections for the different configuration modes.
IREF Pin
The IREF pin is used to set the overcurrent and overload
monitoring threshold. The design requires a 100kΩ
resistor to connect from this pin to ground.
Configuration Assignment Pin Differences
There are two pairs of pins used for configuration
assignments. Both pin pairs are used for the assignment,
and their settings must both match their requirements
for the configuration mode. These pin pairs are:
• OCFG0, OCFG1: define the output stage topology
and operation of the output configuration.
• nERROR/CFG0, PSSYNC/CFG1: define the audio
processing and amplifier control supporting the
output configuration.
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FN6785.0
July 29, 2010