D2-45057_14 Datasheet, PDF (4/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Absolute Maximum Ratings
Supply Voltage
HVDD[A:D], VDDHV. . . . . . . . . . . . . . . . -0.3V to +28.0V
RVDD, PWMVDD . . . . . . . . . . . . . . . . . . . . -0.3V to 4.0V
CVDD, PLLVDD . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.4V
Input Voltage
Any Input but XTALI . . . . . . . . . . . . -0.3V to RVDD +0.3V
XTALI . . . . . . . . . . . . . . . . . . . . . -0.3V to PLLVDD +0.3V
Input Current, Any Pin but Supplies . . . . . . . . . . . . . ±10mA
Thermal Information
Thermal Resistance (Typical)
θ_JA (°C/W) θ_JC (°C/W)
68 Ld QFN Package (Notes 5, 6) . . 25
1
Maximum Storage Temperature . . . . . . . . -55°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . .-10°C to +85°C
High Voltage Supply Voltage,
HVDD[A:D], VDDHV . . . . . . . . . . . . . . . . . . 9.0V to 26.5V
Digital I/O Supply Voltage, PWMVDD . . . . . . . . . . . . . . 3.3V
Core Supply Voltage, CVDD . . . . . . . . . . . . . . . . . . . . 1.8V
Analog Supply Voltage, PLLVDD . . . . . . . . . . . . . . . . . 1.8V
Minimum Load Impedance (HVDD[A:D] ≤24.0V), Z_L . . . . 4Ω
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact
product reliability and result in failures not covered by warranty.
NOTES:
5. θ_JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach”
features. See Tech Brief TB379.
6. For θ_JC, the “case temp” location is the center of the exposed metal pad on the package underside.
7. Absolute Maximum parameters are not tested in production.
Electrical Specifications T_A = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core running at
147.456MHz with typical audio data traffic.
PARAMETER
TEST
CONDITIONS
SYMBOL
MIN
TYP MAX UNIT
Digital Input High Logic Level (Note 8)
Digital Input Low Logic Level (Note 8)
High Level Output Drive Voltage
(I_OUT at -Pin Drive Strength Current)
Low Level Output Drive Voltage
(I_OUT at +Pin Drive Strength Current)
High Level Input Drive Voltage XTALI Pin
Low Level Input Drive Voltage XTALI Pin
Input Leakage Current (Note 9)
Input Capacitance
V_IH
2
-
V_IL
-
-
V_OH RVDD - 0.4
-
-
V
0.8
V
-
V
V_OL
-
-
0.4
V
V_IHX
0.7
V_ILX
-
I_IN
-
Cin
-
- PLLVDD V
-
0.3
V
-
±10 µA
9
-
pF
Output Capacitance
All Outputs Except
Cout
-
OUT[A:D]
9
-
pF
OUT[A:D]
-
190
-
pF
nRESET Pulse Width
Internal Pull-Up Resistance to PWMVDD
(for nERROR0-3, OCFG, nPDN)
t_RST
-
10
-
ns
-
-
100
-
kΩ
Digital I/O Supply Pin Voltage, Current
RVDD
3
Active Current
and
PWMVDD
-
Power-Down Current
-
3.3
10
0.01
3.6
V
-
mA
-
mA
Core Supply Pins
CVDD
1.7
1.8
1.9
V
Active Current
-
300
-
mA
Power-Down Current
(Note 10)
-
6
-
mA
4
FN6785.0
July 29, 2010