D2-45057_14 Datasheet, PDF (18/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Compressed digital formats are not decoded within the
D2-45057, D2-45157 devices. But a bit-exact
pass-through mode is supported from the SPDIFRX input
to the SPDIFTX output, allowing for designs that require
IEC61937-compliant original compressed audio input
bitstream be made available at the product’s S/PDIF
Digital output.
Sample Rate Converter
The D2-45057, D2-45157 devices contain a 2-channel
asynchronous sample rate converter (SRC) within the
audio input signal flow path. This SRC is used to convert
audio data input sampled at one input sample rate, to a
fixed 48kHz output sample rate, aligning asynchronous
input audio streams to a single rate for system
processing.
Audio data presented to the SRC can be from either the
SAI or S/PDIF Digital input sources, with an input sample
rate from 16kHz to 192kHz. In addition to converting the
input sample rate to the output sample rate, input clock
jitter and sampling jitter is attenuated by the SRC,
further enhancing audio quality.
DSP
A 24-bit fixed-point Digital Signal Processor (DSP)
controls the majority of audio processing and system
control functions within the D2-45057, D2-45157
devices.
Audio path signal routing, programmable-parameter
processing blocks, and control logic are defined within
the device’s internal firmware. Signal flows through the
device are buffered and processed through hardware
specific-function blocks, such as the Sample Rate
Converter. Internal device registers allow full integration
of DSP control with the internal ROM-based firmware, as
well as providing for external control of audio processing
parameters.
Clock and PLL
Clock is generated on-chip, using a fundamental-mode
crystal connected across the XTALI and XTALO pins.
XTALO is an output, but is designed only to drive the
crystal, and not connect to any other circuit. XTALI is an
input, connecting to the other side of the crystal.
The clock generation contains a low jitter PLL to ensure
low noise PWM output, and a precise master clock source
for sample rate conversion and the audio processing data
paths. The internal PLL’s VCO clock operates at 12x the
crystal frequency (12 x 24.576MHz) and provides
complete device and system timing reference. It is used
throughout the device, including clock generators for
brown-out detection, system and power-on reset, DSP,
S/PDIF Digital transmitter, and PWM engine timing.
Clock and PLL hardware functions are controlled by
internal device firmware. They are not programmable
and are optimized for device and system operation.
Timers
There are two independent timers used for device and
system control. One timer is used for internal references
for chip-specific operations. The other is used for the
system/board temperature sensing control algorithm.
There are two I/O pins (TIO0 and TIO1) associated with
the timers. Their pin functions are defined by the device
firmware. Only TIO0 is actually used in relationship to its
timer, Timer 0, and operates the timing-related I/O
functions of the temperature monitoring algorithm.
Timer 1 is used for internal functions of the device. Its
pin (TIO1) is not used for this timing operation and is
defined by device firmware as the nMUTE input pin.
Audio Outputs
Audio outputs are provided through four output power
stages, configurable for driving loudspeakers. Three
additional PWM outputs are also available for driving
line-level audio outputs. Combinations of outputs and
their audio processing channel assignment is defined by
the device’s configuration mode settings.
Output Power Stages
The devices include four independent output stages
(Figure 13) that are each implemented using a high-side
(to positive HVDD supply) and a low-side (to HV supply
ground) FET pair. Drivers and overcurrent monitoring are
included in each of these four output stages. Depending
on the selected configuration mode, these four stages
can be used independently as single half-bridge outputs,
or as pairs for full-bridge outputs.
Audio processing PWM channel outputs are routed to the
inputs of the four output stages based on the OCFG0 and
OCFG1, and nERROR/CFG0 and PSSYNC/CFG1
configuration settings. Each output stage includes its own
high-side and low-side current sensing that feeds to
internal monitor logic as well as providing its nERROR
output connection. Temperature and undervoltage
monitoring also provides status and input to device
protection control.
HSBSA
HIGH-SIDE
PWM DRIVE
LOW SIDE
PWM DRIVE
HIGH
SIDE
FET
LOW
SIDE
FET
(+)
HVDD
OUT
(GND)
HGND
nERROR
OVERCURRENT
FIGURE 13. OUTPUT STAGE
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FN6785.0
July 29, 2010