D2-45057_14 Datasheet, PDF (7/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Two-Wire (I²C) Interface Port Timing T_A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V
±10%. All grounds at 0.0V. All voltages referenced to ground.
SYMBOL
DESCRIPTION
MIN
MAX
UNIT
f_SCL
SCL Frequency
t_buf
Bus Free Time Between Transmissions
t_wlowSCLx
SCL Clock Low
t_whighSCLx SCL Clock High
t_sSTA
Setup Time For a (Repeated) Start
t_hSTA
Start Condition Hold Time
t_hSDAx
SDA Hold From SCL Falling (Note 11)
t_sSDAx
SDA Setup Time to SCL Rising
t_dSDAx
SDA Output Delay Time From SCL Falling
t_r
Rise Time of Both SDA and SCL (Note 12)
t_f
Fall Time of Both SDA and SCL (Note 12)
t_sSTO
Setup Time For a Stop Condition
NOTES:
11. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
12. Limits established by characterization and not production tested.
-
100
4.7
-
4.7
-
4.0
-
4.7
-
4.0
-
1 (typical)
250
-
-
3.5
-
1
-
300
4.7
-
kHz
µs
µs
µs
µs
µs
sys clk
ns
µs
µs
ns
µs
twhighSCLx
twlowSCLx
SCLx
tr
tf
tsSTA
SDAx
(INPUT)
SDAx
(OUTPUT)
thSDAx
tsSTO
tsSDAx
tbuf
thSTAx
tdSDAx
FIGURE 2. I²C INTERFACE TIMING
7
FN6785.0
July 29, 2010