D2-45057_14 Datasheet, PDF (13/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Pin Description (Continued)
PIN
VOLTAGE
NAME
LEVEL
PIN (Note 13) TYPE (V)
DESCRIPTION
65 VOL0/ I/O
nSS
3.3 Volume control pulse input and SPI slave select. At de-assertion of device reset, pin operates
as SPI slave select input. Then upon internal D2-45057, D2-45157 firmware execution, pin
becomes input for monitoring up/down phase pulses from volume control. (1 of 2 volume
input pins.)
66 CGND
P
1.8 Core ground
67 CVDD
P
1.8 Core power, +1.8VDC. Used in the chip internal DSP, logic and interfaces.
68 nRSTOUT O
3.3 Active low open drain output, with 16mA drive strength. Pin drives low from RVDD 3.3V
brownout detector, PWMVDD 3.3V brownout detector, or 1.8V brownout detector going
active. This output should be used to initiate a system reset to the nRESET pin upon
brownout event detection.
NOTES:
13. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix, such as nRESET.
14. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be
tied together, CGND pins to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) Also, CGND
and RGND are to be tied together on board, and RGND and PWMGND pins are internally connected and are to be tied together
on the board.
15. Thermal pad is internally connected to all 4 HGND ground pins (HGNDA, HGNDB, HGNDC, HGNDD). Any connection to the
thermal pad must be made to the common ground for these 4 ground pins.
13
FN6785.0
July 29, 2010