D2-45057_14 Datasheet, PDF (6/31 Pages) Intersil Corporation – Intelligent Digital Amplifier PWM Controller and Audio Processor

D2-45057, D2-45157
Performance Specifications T_A = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%,
RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz,
core running at 147.456MHz with typical audio data traffic.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
r_DS(ON) (Maximum, MOSFETs @ +25°C)
r_DS(ON) Mismatch
PWM Switching Rate
r_DS(ON)
-
-
-
200
1
384
-
mΩ
-
%
-
kHz
nPDN Input Off Delay
nPDN Input On Delay
POWER OUTPUT
t_PDNOFF
-
1.4
-
ms
t_PDNON
-
1.4
-
ms
<1% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
P_OUT
-
25
-
W
<10% THD, Bridged, Load = 8Ω, HVDD[A:D] = 24V
P_OUT
-
30
-
W
<1% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
P_OUT
-
7
-
W
<10% THD, Half-Bridge, Load = 8Ω, HVDD[A:D] = 24V
P_OUT
-
9
-
W
THD+N
Load = 8Ω, Power = 25W, Bridged, 1kHz
THD+N
-
0.3
-
%
Load = 8Ω, Power = 1W, Bridged, 1kHz
-
0.05
-
%
SNR
SNR
-
110
-
dB
Efficiency (Power Stage, Load = 8Ω)
-
90
-
%
Serial Audio Interface Port Timing T_A = +25°C, HVDD[A:D]/VDDHV = 24V, CVDD = PLLVDD = 1.8V ±5%,
RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. PLL at 294.912MHz, OSC at 24.576MHz, core
running at 147.456MHz with typical audio data traffic.
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNIT
t_cSCLK
t_wSCLK
t_sLRCLK
t_hLRCLK
t_sSDI
t_hSDI
SCLK Frequency - (SCLK)
SCLK Pulse Width (high and low) - (SCLK)
LRCKR Setup to SCLK Rising - (LRCK)
LRCKR Hold from SCLK Rising - (LRCK)
SDIN Setup to SCLK Rising - (SDIN)
SDIN Hold from SCLK Rising - (SDIN)
-
-
12.5
MHz
40
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
20
-
-
ns
SCLK
tcSCLK
thLRCLK
LRCK
SDIN
tsLRCLK
twSCLK
twSCLK
tsSDI
thSDI
FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING
6
FN6785.0
July 29, 2010