80C86_06 Datasheet, PDF (8/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

80C86
accesses; one, if the word operand is on an even byte
boundary and two, if it is on an odd byte boundary. Except
for the performance penalty, this double access is transpar-
ent to the software. The performance penalty does not occur
for instruction fetches; only word operands.
Physically, the memory is organized as a high bank (D15-
D8) and a low bank (D7-D0) of 512K bytes addressed in par-
allel by the processor’s address lines.
Byte data with even addresses is transferred on the D7-D0
bus lines, while odd addressed byte data (A0 HIGH) is trans-
ferred on the D15-D8 bus lines. The processor provides two
enable signals, BHE and A₀, to selectively allow reading
from or writing into either an odd byte location, even byte
location, or both. The instruction stream is fetched from
memory as words and is addressed internally by the proces-
sor at the byte level as necessary.
In referencing word data, the BlU requires one or two memory
cycles depending on whether the starting byte of the word is
on an even or odd address, respectively. Consequently, in ref-
erencing word operands performance can be optimized by
locating data on even address boundaries. This is an espe-
cially useful technique for using the stack, since odd address
references to the stack may adversely affect the context
switching time for interrupt processing or task multiplexing.
Certain locations in memory are reserved for specific CPU
operations (See Figure 2). Locations from address FFFF0H
through FFFFFH are reserved for operations including a jump
to the initial program loading routine. Following RESET, the
CPU will always begin execution at location FFFF0H where
the jump must be located. Locations 00000H through 003FFH
are reserved for interrupt operations. Each of the 256 possible
interrupt service routines is accessed thru its own pair of 16-
bit pointers (segment address pointer and offset address
pointer). The first pointer, used as the offset address, is
loaded into the lP and the second pointer, which designates
the base address is loaded into the CS. At this point program
control is transferred to the interrupt routine. The pointer ele-
ments are assumed to have been stored at the respective
places in reserved memory prior to occurrence of interrupts.
Minimum and Maximum Operation Modes
The requirements for supporting minimum and maximum
80C86 systems are sufficiently different that they cannot be
met efficiently using 40 uniquely defined pins. Consequently,
the 80C86 is equipped with a strap pin (MN/MX) which
defines the system configuration. The definition of a certain
subset of the pins changes, dependent on the condition of the
strap pin. When the MN/MX pin is strapped to GND, the
80C86 defines pins 24 through 31 and 34 in maximum mode.
When the MN/MX pin is strapped to V_CC, the 80C86 gener-
ates bus control signals itself on pins 24 through 31 and 34.
The minimum mode 80C86 can be used with either a multi-
plexed or demultiplexed bus. This architecture provides the
80C86 processing power in a highly integrated form.
The demultiplexed mode requires two 82C82 latches (for 64K
addressability) or three 82C82 latches (for a full megabyte of
addressing). An 82C86 or 82C87 transceiver can also be
used if data bus buffering is required. (See Figure 6A.) The
80C86 provides DEN and DT/R to control the transceiver, and
ALE to latch the addresses. This configuration of the minimum
mode provides the standard demultiplexed bus structure with
heavy bus buffering and relaxed bus timing requirements.
The maximum mode employs the 82C88 bus controller (See
Figure 6B). The 82C88 decodes status lines S0, S1 and S2,
and provides the system with all bus control signals.
Moving the bus control to the 82C88 provides better source
and sink current capability to the control lines, and frees the
80C86 pins for extended large system features. Hardware
lock, queue status, and two request/grant interfaces are pro-
vided by the 80C86 in maximum mode. These features allow
coprocessors in local bus and remote bus configurations.
Bus Operation
The 80C86 has a combined address and data bus com-
monly referred to as a time multiplexed bus. This technique
provides the most efficient use of pins on the processor
while permitting the use of a standard 40 lead package. This
“local bus” can be buffered directly and used throughout the
system with address latching provided on memory and I/O
modules. In addition, the bus can also be demultiplexed at
the processor with a single set of 82C82 address latches if a
standard non-multiplexed bus is desired for the system.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4 (see Fig-
ure 3). The address is emitted from the processor during T1
and data transfer occurs on the bus during T3 and T4. T2 is
used primarily for changing the direction of the bus during
read operations. In the event that a “NOT READY” indication
is given by the addressed device, “Wait” states (TW) are
inserted between T3 and T4. Each inserted wait state is the
same duration as a CLK cycle. Periods can occur between
80C86 driven bus cycles. These are referred to as idle”
states (T_I) or inactive CLK cycles. The processor uses these
cycles for internal housekeeping and processing.
During T1 of any bus cycle, the ALE (Address Latch Enable)
signal is emitted (by either the processor or the 82C88 bus
controller, depending on the MN/MX strap). At the trailing
edge of this pulse, a valid address and certain status infor-
mation for the cycle may be latched.
Status bits S0, S1 and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
TABLE 2.
S2
S1
S0
CHARACTERISTICS
0
0
0 Interrupt
0
0
1 Read I/O
0
1
0 Write I/O
0
1
1 Halt
1
0
0 Instruction Fetch
1
0
1 Read Data from Memory
1
1
0 Write Data to Memory
1
1
1 Passive (No Bus Cycle)
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