80C86_06 Datasheet, PDF (21/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

80C86
AC Electrical Specifications
V_CC = 5.0V ±10%
V_CC = 5.0V ±10%;
V_CC = 5.0V ±10%;
V_CC = 5.0V ±5%;
T_A = 0^oC to +70^oC (C80C86, C80C86-2)
T_A = -40^oC to +85^oC (I80C86, I80C86-2)
T_A = -55^oC to +125^oC (M80C86)
T_A = -55^oC to +125^oC (M80C86-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
TIMING REQUIREMENTS
80C86
80C86-2
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX UNITS TEST CONDITIONS
(1) TCLCL CLK Cycle Period
200
125
ns
(2) TCLCH CLK Low Time
118
68
ns
(3) TCHCL CLK High Time
69
44
ns
(4) TCH1CH2 CLK Rise Time
10
10
ns From 1.0V to 3.5V
(5) TCL2CL1 CLK Fall Time
10
10
ns From 3.5V to 1.0V
(6) TDVCL Data in Setup Time
30
20
ns
(7) TCLDX1 Data In Hold Time
10
10
ns
(8) TR1VCL RDY Setup Time into 82C84A
35
35
ns
(Notes 10, 11)
(9) TCLR1X RDY Hold Time into 82C84A
0
(Notes 10, 11)
0
ns
(10) TRYHCH READY Setup Time into 80C86
118
68
ns
(11) TCHRYX READY Hold Time into 80C86
30
20
ns
(12) TRYLCL READY Inactive to CLK (Note 12)
-8
-8
ns
(13) TlNVCH Setup Time for Recognition (lNTR,
30
15
ns
NMl, TEST) (Note 11)
(14) TGVCH RQ/GT Setup Time
30
15
ns
(15) TCHGX RQ Hold Time into 80C86 (Note 13)
40 TCHCL+ 30 TCHCL+ ns
10
10
(16) TILlH Input Rise Time (Except CLK)
15
15
ns From 0.8V to 2.0V
(17) TIHIL Input Fall Time (Except CLK)
15
15
ns From 2.0V to 0.8V
TIMING RESPONSES
(18) TCLML Command Active Delay (Note 10)
5
35
5
35
ns C_L = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(19) TCLMH Command Inactive (Note 10)
5
35
5
35
ns C_L = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(20) TRYHSH READY Active to Status Passive
(Notes 12, 14)
110
65
ns C_L = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(21) TCHSV Status Active Delay
10
110
10
60
ns C_L = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
(22) TCLSH Status Inactive Delay (Note 14)
10
130
10
70
ns C_L = 100pF for All
80C86 Outputs (In
Addition to 80C86
Self Load)
161