80C86_06 Datasheet, PDF (11/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

80C86
External Interface
Processor RESET and Initialization
Processor initialization or start up is accomplished with activa-
tion (HIGH) of the RESET pin. The 80C86 RESET is required to
be HIGH for greater than 4 CLK cycles. The 80C86 will termi-
nate operations on the high-going edge of RESET and will
remain dormant as long as RESET is HIGH. The low-going
transition of RESET triggers an internal reset sequence for
approximately 7 clock cycles. After this interval, the 80C86
operates normally beginning with the instruction in absolute
location FFFF0H. (See Figure 2). The RESET input is internally
synchronized to the processor clock. At initialization, the HIGH-
to-LOW transition of RESET must occur no sooner than 50μs
(or 4 CLK cycles, whichever is greater) after power-up, to allow
complete initialization of the 80C86.
NMl will not be recognized prior to the second CLK cycle follow-
ing the end of RESET. If NMl is asserted sooner than nine clock
cycles after the end of RESET, the processor may execute one
instruction before responding to the interrupt.
Interrupt Operations
Interrupt operations fall into two classes: software or hard-
ware initiated. The software initiated interrupts and software
aspects of hardware interrupts are specified in the Instruc-
tion Set Description. Hardware interrupts can be classified
as non-maskable or maskable.
Interrupts result in a transfer of control to a new program loca-
tion. A 256-element table containing address pointers to the
interrupt service program locations resides in absolute loca-
tions 0 through 3FFH, which are reserved for this purpose.
Each element in the table is 4 bytes in size and corresponds
to an interrupt “type”. An interrupting device supplies an 8-bit
type number during the interrupt acknowledge sequence,
which is used to “vector” through the appropriate element to
the new interrupt service program location. All flags and both
the Code Segment and Instruction Pointer register are saved
as part of the lNTA sequence. These are restored upon exe-
cution of an Interrupt Return (IRET) instruction.
Non-Maskable Interrupt (NMI)
Bus Hold Circuitry
To avoid high current conditions caused by floating inputs to
CMOS devices and to eliminate need for pull-up/down resistors,
“bus-hold” circuitry has been used on the 80C86 pins 2-16, 26-
32 and 34-39. (See Figure 4A and Figure 4B). These circuits
will maintain the last valid logic state if no driving source is
present (i.e., an unconnected pin or a driving source which goes
to a high impedance state). To overdrive the “bus hold” circuits,
an external driver must be capable of supplying approximately
400μA minimum sink or source current at valid input voltage
levels. Since this “bus hold” circuitry is active and not a “resis-
tive” type element, the associated power supply current is negli-
gible and power dissipation is significantly reduced when
compared to the use of passive pull-up resistors.
OUTPUT
DRIVER
BOND
PAD
EXTERNAL
PIN
The processor provides a single non-maskable interrupt pin
(NMI) which has higher priority than the maskable interrupt
request pin (INTR). A typical use would be to activate a
power failure routine. The NMI is edge-triggered on a LOW-
to-HIGH transition. The activation of this pin causes a type 2
interrupt.
NMl is required to have a duration in the HIGH state of
greater than two CLK cycles, but is not required to be syn-
chronized to the clock. Any positive transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves of a block-type instruc-
tion. Worst case response to NMI would be for multiply,
divide, and variable shift instructions. There is no specifica-
tion on the occurrence of the low-going edge; it may occur
before, during or after the servicing of NMI. Another positive
edge triggers another response if it occurs after the start of
the NMI procedure. The signal must be free of logical spikes
in general and be free of bounces on the low-going edge to
avoid triggering extraneous responses.
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 4A. BUS HOLD CIRCUITRY PIN 2-16, 34-39
OUTPUTV^CC
P
DRIVER
BOND
PAD
EXTERNAL
PIN
INPUT
BUFFER
INPUT
PROTECTION
CIRCUITRY
FIGURE 4B. BUS HOLD CIRCUITRY PIN 26-32
Maskable Interrupt (INTR)
The 80C86 provides a single interrupt request input (lNTR)
which can be masked internally by software with the reset-
ting of the interrupt enable flag (IF) status bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK. To
be responded to, lNTR must be present (HIGH) during the
clock period preceding the end of the current instruction or
the end of a whole move for a block type instruction. lNTR
may be removed anytime after the falling edge of the first
INTA signal. During the interrupt response sequence further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (lNTR, NMI, software interrupt or
single-step), although the FLAGS register which is automati-
cally pushed onto the stack reflects the state of the proces-
sor prior to the interrupt. Until the old FLAGS register is
restored, the enable bit will be zero unless specifically set by
an instruction.
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