80C86_06 Datasheet, PDF (17/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

80C86
AC Electrical Specifications
MINIMUM COMPLEXITY SYSTEM
V_CC = 5.0V ±10%; T_A = 0^oC to +70^oC (C80C86, C80C86-2)
V_CC = 5.0V ±100%; T_A = -40^oC to +85^oC (I80C86, I80C86-2)
V_CC = 5.0V ±100%; T_A = -55^oC to +125^oC (M80C86)
V_CC = 5.0V ±5%; T_A = -55^oC to +125^oC (M80C86-2) (Continued)
SYMBOL
PARAMETER
80C86
MIN
MAX
80C86-2
MIN
MAX UNITS
TEST
CONDITIONS
(6) TDVCL Data In Setup Time
30
20
ns
(7) TCLDX1 Data In Hold Time
10
10
ns
(8) TR1VCL RDY Setup Time into 82C84A
35
(Notes 7, 8)
35
ns
(9) TCLR1X RDY Hold Time into 82C84A
0
(Notes 7, 8)
0
ns
(10) TRYHCH READY Setup Time into 80C86
118
68
ns
(11) TCHRYX READY Hold Time into 80C86
30
20
ns
(12) TRYLCL READY Inactive to CLK (Note 9)
-8
-8
ns
(13) THVCH HOLD Setup Time
35
20
ns
(14) TINVCH lNTR, NMI, TEST Setup Time
30
(Note 8)
15
ns
(15) TILIH Input Rise Time (Except CLK)
15
15
ns From 0.8V to 2.0V
(16) TIHIL Input FaIl Time (Except CLK)
15
15
ns From 2.0V to 0.8V
TIMING RESPONSES
(17) TCLAV Address Valid Delay
(18) TCLAX Address Hold Time
(19) TCLAZ Address Float Delay
(20) TCHSZ Status Float Delay
(21) TCHSV Status Active Delay
(22) TLHLL ALE Width
(23) TCLLH ALE Active Delay
(24) TCHLL ALE Inactive Delay
(25) TLLAX Address Hold Time to ALE Inactive
(26) TCLDV Data Valid Delay
(27) TCLDX2 Data Hold Time
(28) TWHDX Data Hold Time After WR
(29) TCVCTV Control Active Delay 1
(30) TCHCTV Control Active Delay 2
10
10
TCLAX
10
TCLCH-20
TCHCL-10
10
10
TCLCL-30
10
10
110
10
60
10
80
TCLAX
50
80
50
110
10
60
TCLCH-10
80
50
85
55
TCHCL-10
110
10
60
10
TCLCL-30
110
10
70
110
10
60
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
ns C_L = 100pF
157