80C86_06 Datasheet, PDF(14/37 Page) Intersil Corporation

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80C86_06 Datasheet, PDF (14/37 Pages) Intersil Corporation – CMOS 16-Bit Microprocessor

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80C86

Bus Timing - Medium Size Systems

For medium complexity systems the MN/MX pin is con-

nected to GND and the 82C88 Bus Controller is added to the

system as well as an 82C82/82C83 latch for latching the

system address, and an 82C86/82C87 transceiver to allow

for bus loading greater than the 80C86 is capable of han-

dling. Signals ALE, DEN, and DT/R are generated by the

82C88 instead of the processor in this configuration,

although their timing remains relatively the same. The

80C86 status outputs (S2, S1 and S0) provide type-of-cycle

information and become 82C88 inputs. This bus cycle infor-

mation specifies read (code, data or I/O), write (data or I/O),

interrupt acknowledge, or software halt. The 82C88 issues

control signals specifying memory read or write, I/O read or

write, or interrupt acknowledge. The 82C88 provides two

types of write strobes, normal and advanced, to be applied

as required. The normal write strobes have data valid at the

leading edge of write. The advanced write strobes have the

same timing as read strobes, and hence, data is not valid at

the leading edge of write. The 82C86/82C87 transceiver

receives the usual T and OE inputs from the 82C88 DT/R

and DEN signals.

The pointer into the interrupt vector table, which is passed

during the second INTA cycle, can be derived from an

82C59A located on either the local bus or the system bus. If

the master 82C59A Priority Interrupt Controller is positioned

on the local bus, the 82C86/82C87 transceiver must be dis-

abled when reading from the master 82C59A during the

interrupt acknowledge sequence and software âpollâ.

VCC

GND

VCC

82C8A/85

CLOCK

GENERATOR

RES

RDY

MN/MX

M/IO

CLK INTA

READY RD

RESET

DT/R

DEN

WAIT

STATE

GENERATOR

ALE

80C86

CPU

GND

AD0-AD15

A16-A19

GND

BHE

40 VCC

C1 = C2 = 0.1Î¼F

VCC

GND

ADDR/DATA

STB

82C82

LATCH

2 OR 3

82C86

TRANSCEIVER

(2)

DATA

BHE

ADDR

OPTIONAL

FOR INCREASED

DATA BUS DRIVE

HM-6516

CMOS RAM

2K x 8 2K x 8

HM-6616

CMOS PROM (2)

2K x 8 2K x 8

CS RD WR

CMOS

82CXX

PERIPHERALS

FIGURE 6A. MINIMUM MODE 80C86 TYPICAL CONFIGURATION

154

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