X45620 Datasheet, PDF (7/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

S₀, S₁, and WP Pin Timing
X45620
SCL
SDA IN
S₀, S₁ and WP
Clk 1
Slave Address Byte
Clk 9
t_{SU: S0, S1, WP}
t_{HD: S0, S1, WP}
Write Cycle Limits
Symbol
T_WC(8)
Parameter
Write Cycle Time
Min
Typ ⁽⁶⁾
Max
—
5
10
Unit
Test Conditions
ms
Note 4
Notes: (8) t_WC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time
the device requires to automatically complete the internal write operation.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal erase/write
cycle. During the write cycle, the X45620 bus interface circuits are disabled, SDA is allowed to remain HIGH, and the
device does not respond to its slave address.
Write Cycle Timing
SCL
SDA
8^th Bit
Word n
ACK
t_WC
Stop
Condition
Start
Condition
7
FN8250.0
July 29, 2005