X45620 Datasheet, PDF (10/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
WDO Output Timing
Symbol
t_WDO
t_RST
Parameter
Watchdog Time Out Period,
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
Reset Time Out
Min Typ (6) Max
75
150
250
200
400
600
500
800
1200
75
150
250
Unit Test Conditions
ms
ms
Note 4
ms
Note 4
ms
PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X45620 activates a Power-
on Reset Circuit. This circuit goes active at about 1V
and pulls the RESET pin active. This signal prevents
the system microprocessor from starting to operate
with insufficient voltage or prior to stabilization of the
oscillator. When Vcc exceeds the device V_TRIP1 value
for t_PURST the circuit releases RESET, allowing the
processor to begin executing code.
Low V_CC (V1MON) Voltage Monitoring
During operation, the X45620 monitors the V_CC level
and asserts RESET if supply voltage falls below a pre-
set minimum V_TRIP1. During this time the communica-
tion to the device is interrupted. The RESET signal also
prevents the microprocessor from operating in a power
fail or brownout condition. The RESET signal remains
active until the voltage drops below 1V. RESET also
remains active until V_CC returns and exceeds V_TRIP1
for t_PURST.
Low V2MON Voltage Monitoring
The X45620 also monitors a second voltage level and
asserts V2FAIL if the voltage falls below a preset mini-
mum V_TRIP2. The V2FAIL signal is either ORed with
Figure 1. Two Uses of Dual Voltage Monitoring
RESET to prevent the microprocessor from operating
in a power fail or brownout condition or used to inter-
rupt the microprocessor with notification of an impend-
ing power failure. The V2FAIL signal remains active
until V2MON returns and exceeds V_TRIP2.
The V2MON circuit is powered by V_CC (or V_BATT). If
both V_CC and V_BATT are at or below Vtrip, V2MON will
not be monitored.
Watchdog Timer
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring SDA and SCL pin. In normal
operation, the microprocessor must periodically restart
the Watchdog Timer to prevent WDO from going
active. The watchdog timer is restarted on the first
HIGH to LOW transition on SCL after a start com-
mand. The start command is defined as SDA going
HIGH to LOW while SCL is HIGH. The state of two
nonvolatile control bits in the Status Register deter-
mines the watchdog timer period. The microprocessor
can change these watchdog bits by writing to the sta-
tus register. The factory default setting disables the
watchdog timer.
The Watchdog Timer oscillator stops and resets when
in battery backup mode. It re-starts when V_CC returns.
Unregulated
Supply
R1
R2
X45620
V_OUT
5V
Reg
V_CC
RESET
V2MON
V2FAIL
System
Reset
System
Interrupt
R1 and R2 selected so V2 = V2MON threshold when
Unregulated supply reaches 6V.
Unregulated
Supply
5V
Reg
3.0V
Reg
X45620
V_CC
RESET
V2MON
V2FAIL
V_OUT
System
Reset
Notice: No external components required to monitor
two voltages.
10
FN8250.0
July 29, 2005