X45620 Datasheet, PDF (3/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
PIN DESCRIPTION (Continued)
Pin Name
8
RESET
/MR
9
WDO
10
V_SS
11
SDA
14
12–13
15
SCL
NC
V_BATT
16
V_OUT
17 BATT-ON
18
NC
19
WP
20
V_CC
(V1MON)
Function
Reset Output/Manual Reset Input. This is an Input/Output pin.
RESET Output. This is an active LOW, open drain output which goes active whenever V_CC falls
below the minimum V_CC sense level. When RESET is active communication to the device is interrupt-
ed. RESET remains active until V_CC rises above the minimum V_CC sense level for t_PURST. RESET
also goes active on power-up and remains active for t_PURST after the power supply stabilizes.
MR Input. This is an active LOW debounced input. When MR is active, the RESET pins are assert-
ed. When MR is released, the RESET remains asserted for t_PURST, and then released.
Watchdog Output. WDO is an active low, open drain output which goes active whenever the
watchdog timer goes active. WDO remains active for 150ms, then returns to the inactive state.
Ground
Serial Data. SDA is a bidirectional pin used to transfer data into and out of the device. It is an open
drain output, requires the use of a pull-up resistor.
Serial Clock. The SCL input is used to clock all data into and out of the device.
No internal connections
Battery Supply Voltage. This input provides a backup supply in the event of a failure of the pri-
mary V_CC voltage. The V_BATT voltage typically provides the supply voltage necessary to maintain
the contents of SRAM and also powers the internal logic to “stay awake.” If unused, connect V_BATT
to ground.
Output Voltage.
V_OUT = V_CC if V_CC > V_TRIP1.
IF V_CC < V_TRIP1, then,
V_OUT = V_CC if V_CC > V_BATT+0.03
V_OUT = V_BATT if V_CC < V_BATT-0.03
Note: There is hysteresis around V_BATT ± 0.03V point to avoid oscillation at or near the
switchover voltage. A capacitance of 0.1µF must be connected to Vout to ensure stability.
Battery On. This CMOS output goes HIGH when the V_OUT switches to V_BATT and goes LOW
when V_OUT switches to V_CC. It is used to drive a external P-channel FET when V_CC = V_OUT and
current requirements are greater than 50mA.
The purpose of this output is to drive an external FET to get higher operating currents when the
V_CC supply is fully functional. In the event of a V_CC failure, the battery voltage is applied to the
V_OUT pin and the external transistor is turned off. In this “backup condition,” the battery only needs
to supply enough voltage and current to keep SRAM devices from losing their data-there is no
communication at this time.
No Connect
Write Protect. The WP pin works in conjunction with a nonvolatile WPEN bit to “lock” the setting
of the Watchdog Timer control and the memory write protect bits. This pin has an internal pull down
resistor. (>10MΩ typical)
Supply Voltage/V1 Voltage Monitor Input. When the V1MON input is less than the VTRIP1
voltage, RESET and LOWLINE go ACTIVE.
3
FN8250.0
July 29, 2005