X45620 Datasheet, PDF (6/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Read & Write Cycle Limits
Symbol
Parameter
Min
f_SCL
SCL clock frequency
t_IN
Pulse width suppression time at inputs
50
t_AA
SCL LOW to SDA Data Out Valid
0.1
t_BUF
Time the bus must be free before a new transmission can start 1.3
t_LOW
Clock LOW period
1.3
t_HIGH
Clock HIGH period
0.6
t_SU:STA Start condition setup time
0.6
t_HD:STA Start condition hold time
0.6
t_SU:DAT Data in setup time
100
t_HD:DAT Data in hold time
0
t_SU:STO Stop condition setup time
0.6
t_DH
Data output hold time
50
Max
400
0.9
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
Test Conditions
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Note 4
Serial Output Timing
Symbol
t_R
t_F
t_{SU:S0, S1, WP}
t_{HD:S0, S1, WP}
Cb
Parameter
SDA and SCL rise time
SDA and SCL fall time
S0, S1, and WP Setup Time
S0, S1, and WP Hold Time
Capacitive load for each bus line
Min
20 + .1Cb
20 + .1Cb
0.6
0
Max
300
300
400
Unit
ns
ns
ns
ns
pF
Test Conditions
Note 4
Note 4
Note 4
Note 4
Note 4, 7
POWER-UP TIMING ⁽⁵⁾
Symbol
t_PUR
t_PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
5
Unit
ms
ms
Test Conditions
Note 4
Note 4
Notes: (5) t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated. These parameters are
not 100% tested.
(6) Typical values are for T_A = 25°C and nominal supply voltage (5V)
(7) Cb = total capacitance of one bus line in pF.
Bus Timing
SCL
SDA IN
t_SU:STA
t_F
t_HIGH
t_LOW
t_HD:STA
t_HD:DAT
t_SU:DAT
t_R
t _SU:STO
t_AA
t_DH
t_BUF
SDA OUT
6
FN8250.0
July 29, 2005