X45620 Datasheet, PDF (15/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
The master terminates the data byte loading by issuing
a stop condition, which causes the device to begin the
nonvolatile write cycle. As with the byte write operation,
all inputs are disabled until completion of the internal
write cycle. Refer to Figure 12 for the address,
acknowledge, and data transfer sequence.
Stop and Write Modes
Stop conditions that terminate write operations must
be sent by the master after sending at least 1 full data
byte and it’s associated ACK signal. If a stop is issued
in the middle of a data byte, or before 1 full data byte +
ACK is sent, then the device will reset itself without
performing the write. The contents of the array will not
be affected.
Acknowledge Polling
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the inter-
nal write cycle, then no ACK will be returned. If the
device has completed the internal write operation, an
ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 13.
Figure 11. Byte Write Sequence
Signals from
the Master
S
T
A
R
Slave
Address
T
Word Address
Byte 1
Word Address
Byte 0
S
Data
T
O
P
SDA Bus
S 1 0 1 0 0 S₁S₀ 0
P
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
Figure 12. Page Write Sequence
S
Signals from
the Master
T
A
R
Slave
Address
T
Word Address
Byte 1
Word Address
Byte 0
Data
(0)
SDA Bus ^{S 1 0 1 0 0 S}1^S0 ⁰
Signals from
the Slave
A
A
A
A
C
C
C
C
K
K
K
K
(0 ≤ n ≤ 64)
Data
S
(n)
T
O
P
P
A
C
K
15
FN8250.0
July 29, 2005