X45620 Datasheet, PDF (16/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
Figure 13. Acknowledge Polling Sequence
Byte Load Completed
by Issuing Stop.
Enter ACK Polling
Issue
Start
Issue Slave
Address Byte
(Read or Write)
Issue Stop
ACK
NO
Returned?
YES
High
Voltage
Cycle Complete.
NO
Continue
Sequence?
YES
Continue Normal
Read or Write
Command Sequence?
Issue Stop
PROCEED
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads. Refer to bus tim-
ing on page 21.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last word read or written
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address on the same page.
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the eight bits of the Data Byte. The master ter-
minates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 14 for the
address, acknowledge, and data transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
Note: After a power-up sequence, the first read cannot
be a current address read.
Figure 14. Current Address Read Sequence
S
Signals from
the Master
T
A
R
Slave
Address
S
T
O
T
P
SDA Bus
S 1 0 1 0 0 S₁S₀ 1
P
Signals from
the Slave
A
C
Data
K
Random Read
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues the Word Address Byte 1,
receives another acknowledge, then issues the Word
Address Byte 0. After the device acknowledges receipt
of the Word Address Byte 0, the master issues
another start condition and the Slave Address Byte with
the R/W bit set to one. This is followed by an acknowl-
edge and then eight bits of data from the device. The
master terminates the read operation by not respond-
ing with an acknowledge and then issuing a stop con-
dition. Refer to Figure 9 for the address, acknowledge,
and data transfer sequence.
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the sec-
ond start shown in Figure 15. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the
address counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
16
FN8250.0
July 29, 2005