X45620 Datasheet, PDF (19/20 Pages) Intersil Corporation – Dual Voltage Monitor with Integrated System Battery Switch and EEPROM

X45620
Table 3. Write Protect Enable Bit and WP Pin Function
Memory Array Not Memory Array
WP WPEN Block Protected Block Protected
LOW
X
Writes OK
Writes Blocked
HIGH
0
HIGH
1
Writes OK
Writes OK
Writes Blocked
Writes Blocked
Block Lock Bits
Writes OK
Writes OK
Writes Blocked
WPEN Bit
Writes OK
Writes OK
Writes Blocked
Protection
Software
Software
Hardware
Writing to the Control Register
Changing any of the nonvolatile bits of the control regis-
ter requires the following steps:
– Write a 02H to the CR to set the Write Enable Latch
(WEL). This is a volatile operation, so there is no
delay after the write. (Operation preceeded by a start
and ended with a stop).
– Write a 06H to the CR to set both the Register Write
Enable Latch (RWEL) and the WEL bit. This is also a
volatile cycle. The zeros in the data byte are required.
(Operation preceeded by a start and ended with a
stop).
– Write a value to the CR that has all the control bits set
to the desired state, with the WEL bit set to ‘1’ and the
RWEL bit set to ‘0’. This can be represented as nqrs
t01u in binary, where n is the WPEN bit and qrstu are
the WD1, WD0, BP1, BP0 and PUP bits. (Operation
preceeded by a start and ended with a stop). Since
this is nonvolatile write cycle it will take up to 10ms to
complete. The RWEL bit is reset by this cycle and the
sequence must be repeated to change the nonvolatile
bits again. If bit 2 is set to ‘1’ in this third step (nqrs
t11u) then the RWEL bit remains set and the WPEN,
PUP, WD1, WD0, BP1 and BP0 bits remain
unchanged.
– A read operation occurring between any of the previ-
ous operations will not interrupt the register write
operation.
– The RWEL bit cannot be reset without writing to the
nonvolatile control bits in the control register, power
cycling the device or attempting a write to a write pro-
tected block.
– Changes made to the Control Register non-volatile
bits become effective upon the next read operation of
the control register. (Power cycling will also activate
changes to the control register).
– Changes made to volatile bits in the Register take
effect immediately following the last data bit.
To illustrate, a sequence of writes to the device consist-
ing of [02H, 06H, 02H] will reset all of the nonvolatile
bits to 0 and clear the RWEL bit. A sequence of [02H,
06H, 06H] will leave the nonvolatile bits unchanged and
the RWEL bit remains set.
When resetting the WEL bit, the operation goes active
immediately following the last data bit. The device will,
therefore, not respond with an ACK after the reset WEL
command data byte.
OPERATIONAL NOTES
The device powers-up in the following state:
– The device is in the low power standby state.
– A “Start Bit” is required to enter an active state to
receive an instruction.
– The Write Enable Latch (WEL) is reset.
– The RESET Signal is active for t_PURST.
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
– The WEL bit must be set before writing to the
memory array.
– The WEL and RWEL bits must be set before writing
to the nonvolatile bits of the Control Register.
– A valid slave byte and two address bytes must be
sent to the device with a valid ACK between each
byte.
– A “Stop Bit” must be received following a multiple of
8 data bits and completion of the data ACK bit.
– During the time RESET is active communication to
the device are ignored.
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FN8250.0
July 29, 2005