X5083_06 Datasheet, PDF (6/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
WP
V_P = 15-18V
CS
SCK
SI
0 1 23 4 56 7
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
16 Bits
06h
WREN
02h
Write
0001h
Address
FIGURE 1. SET V_TRIP LEVEL SEQUENCE (V_CC = DESIRED V_TRIP VALUE)
00h
Data
WP
CS
SCK
SI
V_P = 15-18V
0 1 23 4 56 7
0 1 2 3 4 5 6 7 8 9 10 20 21 22 23
16 Bits
06h
WREN
02h
Write
0003h
Address
FIGURE 2. RESET V_TRIP LEVEL SEQUENCE (V_CC > 3V. WP = 15-18V)
00h
Data
V_TRIP
Adj.
V_P
Adjust
Run
1
8
2
7
3 ^X5083 6
4
5
4.7K
RESET
FIGURE 3. SAMPLE V_TRIP RESET CIRCUIT
µC
SCK
SI
SO
CS
6
FN8127.3
June 15, 2006