X5083_06 Datasheet, PDF (1/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

®
Data Sheet
June 15, 2006
X5083
FN8127.3
CPU Supervisor with 8Kbit SPI EEPROM
This device combines four popular functions, Power-on Reset
Control, Watchdog Timer, Supply Voltage Supervision, and
Block Lock Serial EEPROM Memory in one package. This
combination lowers system cost, reduces board space
requirements, and increases reliability.
Applying power to the device activates the power-on reset
circuit which holds RESET active for a period of time. This
allows the power supply and oscillator to stabilize before the
processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller fails to
restart a timer within a selectable time out interval, the device
activates the RESET signal. The user selects the interval
from three preset values. Once selected, the interval does
not change, even after cycling the power.
The device’s low V_CC detection circuitry protects the user’s
system from low voltage conditions, resetting the system
when V_CC falls below the minimum V_CC trip point. RESET is
asserted until V_CC returns to the proper operating level and
stabilizes. Five industry standard V_TRIP thresholds are
available, however, Intersil’s unique circuits allow the threshold
to be reprogrammed to meet custom requirements or to fine-
tune the threshold for applications requiring higher precision.
Pinouts
8 LD TSSOP
RESET
V_CC
CS/WDI
SO
1
8
2
7
X5083
3
6
4
5
SCK
SI
V_SS
WP
8 LD SOIC, 8 LD PDIP
CS/WDI
SO
WP
V_SS
1
8
2
7
3 ^X5083 6
4
5
V_CC
RESET
SCK
SI
Features
• Low V_CC detection and reset assertion
- Four standard reset threshold voltages
4.63V, 4.38V, 2.93V, 2.63V
- Re-program low V_CC reset threshold voltage using
special programming sequence
- Reset signal valid to V_CC = 1V
• Selectable time out watchdog timer
• Long battery life with low power consumption
- <50µA max standby current, watchdog on
- <1µA max standby current, watchdog off
- <400µA max active current during read
• 8Kbits of EEPROM
• Save critical data with Block Lock^™ memory
- Block lock first or last page, any 1/4 or lower 1/2 of
EEPROM array
• Built-in inadvertent write protection
- Write enable latch
- Write protect pin
• SPI Interface - 3.3MHz clock rate
• Minimize programming time
- 16 byte page write mode
- 5ms write cycle time (typical)
• SPI modes (0,0 & 1,1)
• Available packages
- 8 Ld TSSOP, 8 Ld SOIC, 8 Ld PDIP
• Pb-free plus anneal available (RoHS compliant)
Applications
• Communications Equipment
- Routers, Hubs, Switches
- Set Top Boxes
• Industrial Systems
- Process Control
- Intelligent Instrumentation
• Computer Systems
- Desktop Computers
- Network Servers
• Battery Powered Equipment
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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