X5083_06 Datasheet, PDF (17/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
RESET Output Timing
SYMBOL
PARAMETER
V_TRIP
Reset trip point voltage, X5083PT-4.5A (Note 6)
Reset trip point voltage, X5083PT
Reset trip point voltage, X5083PT-2.7A
Reset trip point voltage, X5083PT-2.7
t_PURST
Power-up reset time out
t_RPD (Note 5) V_CC detect to reset/output
t_F (Note 5) V_CC fall time
t_R (Note 5) V_CC rise time
V_RVALID
Reset valid V_CC
NOTES:
5. This parameter is periodically sampled and not 100% tested.
6. PT = Package/Temperature
CS vs. RESET Timing
MIN
TYP
4.5
4.63
4.25
4.38
2.85
2.93
2.55
2.63
100
200
0.1
0.1
1
CS
RESET
t_CST
t_WDO
t_RST
t_WDO
t_RST
MAX
4.75
4.5
3.00
2.7
280
500
UNIT
V
ms
ns
ns
ns
V
RESET Output Timing
SYMBOL
PARAMETER
t_WDO
Watchdog time out period,
WD1 = 1, WD0 = 1(default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
t_CST
CS pulse width to reset the watchdog
t_RST
Reset time out
MIN
TYP
MAX
UNIT
OFF
100
200
300
ms
450
600
800
ms
1
1.4
2
sec
400
ns
100
200
300
ms
17
FN8127.3
June 15, 2006