X5083_06 Datasheet, PDF (10/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Data Protection
The following circuitry has been included to prevent
inadvertent writes:
• A WREN instruction must be issued to set the write enable
latch.
• CS must come HIGH at the proper clock count in order to
start a nonvolatile write cycle.
• When V_CC is below V_TRIP, communications to the device
are inhibited.
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30
Read Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
3210
Data Out
High Impedance
SO
76543210
FIGURE 5. READ OPERATION SEQUENCE
CS
SCK
01234567
...
Read Status
Instruction
SI
...
SO
WW
DD
10
B
L
2
B
L
1
B
L
0
...
SO = Status Reg When no Nonvolatile
Write Cycle
FIGURE 6. READ STATUS OPERATION SEQUENCE
10
FN8127.3
June 15, 2006