X5083_06 Datasheet, PDF (11/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
CS
SCK
SI
01234567
Instruction
(1 Byte)
High Impedance
SO
FIGURE 7. WREN/WRDI SEQUENCE
CS
SCK
SI
0 1 2 3 4 5 6 7 8 9 10
20 21 22 23 24 25 26 27 28 29 30 31
Instruction
16 Bit Address
Data Byte 1
15 14 13
3 2 10 7 65 43 2 10
CS
SCK
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
Data Byte 2
Data Byte 3
SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Data Byte N
654 321 0
FIGURE 8. EEPROM ARRAY WRITE SEQUENCE
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
SI
SO
High Impedance
Data Byte
6 54 3 2 1 0
WW
DD
10
B
L
2
B
L
1
B
L
0
FIGURE 9. STATUS REGISTER WRITE SEQUENCE
11
FN8127.3
June 15, 2006