X5083_06 Datasheet, PDF (4/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Ordering Information (Continued)
PART NUMBER RESET
(ACTIVE LOW)
PART MARKING
X5083P-2.7
X5083P F
V_CC RANGE (V)
2.7-5.5
V_TRIP RANGE
2.55-2.7
TEMPERATURE
RANGE (°C)
PACKAGE
0 to 70
8 Ld PDIP
PKG.
DWG. #
MDP0031
X5083PZ-2.7 (Note)
X5083P ZF
0 to 70
8 Ld PDIP* (Pb-free)
MDP0031
X5083PI-2.7
X5083P G
-40 to 85 8 Ld PDIP
MDP0031
X5083PIZ-2.7 (Note)
X5083P ZG
-40 to 85 8 Ld PDIP* (Pb-free)
MDP0031
X5083S8-2.7*
X5083 F
0 to 70
8 Ld SOIC
MDP0027
X5083S8Z-2.7* (Note)
X5083 ZF
0 to 70
8 Ld SOIC (Pb-free)
MDP0027
X5083S8I-2.7*
X5083 G
-40 to 85 8 Ld SOIC
MDP0027
X5083S8IZ-2.7* (Note)
X5083 ZG
-40 to 85 8 Ld SOIC (Pb-free)
MDP0027
X5083V8-2.7
583 F
0 to 70
8 Ld TSSOP
M8.173
X5083V8Z-2.7 (Note)
583 FZ
0 to 70
8 Ld TSSOP (Pb-free) M8.173
X5083V8I-2.7
583G
-40 to 85 8 Ld TSSOP
M8.173
X5083V8IZ-2.7 (Note)
583 GZ
-40 to 85 8 Ld TSSOP (Pb-free) M8.173
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
*Add "-T1" suffix for tape and reel.
*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
Pin Description
PIN
(SOIC/
PDIP)
1
2
5
6
3
4
8
7
PIN
TSSOP
3
4
7
8
5
6
2
1
NAME
FUNCTION
CS/WDI
Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high impedance state. Unless
a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the
device, placing it in the active power mode. Prior to the start of any operation after power-up, a HIGH to LOW
transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The absence of a
HIGH to LOW transition within the watchdog time out period results in RESET going active.
SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The falling edge of the
serial clock (SCK) clocks the data out.
SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data on this pin. The rising
edge of the serial clock (SCK) latches the input data. Send all opcodes (Table 1), addresses and data MSB first.
SCK
Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising edge of SCK latches
in the opcode, address, or data bits present on the SI pin. The falling edge of SCK changes the data output on the SO
pin.
WP Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited. This “Locks” the
memory to protect it against inadvertent changes when WP is HIGH, the device operates normally.
V_SS
V_CC
RESET
Ground
Supply Voltage
Reset Output. RESET is an active LOW, open drain output which goes active whenever V_CC falls below the
minimum V_CC sense level. It will remain active until V_CC rises above the minimum V_CC sense level for 250ms.
RESET goes active if the watchdog timer is enabled and CS remains either HIGH or LOW longer than the
selectable watchdog time out period. A falling edge of CS will reset the watchdog timer. RESET goes active on
power-up at about 1V and remains active for 250ms after the power supply stabilizes.
4
FN8127.3
June 15, 2006