X5083_06 Datasheet, PDF (15/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Equivalent A.C. Load Circuit at 5V V_CC
5V
5V
SO
OUTPUT
1.64kΩ
1.64kΩ
100pF
RESET
3.3kΩ
30pF
A.C. Test Conditions
Input pulse levels
Input rise and fall times
Input and output timing level
V_CC x 0.1 to V_CC x 0.9
10ns
V_CC x 0.5
AC Electrical Specifications (Over recommended operating conditions, unless otherwise specified)
2.7V-5.5V
SYMBOL
PARAMETER
MIN
MAX
UNIT
DATA INPUT TIMING
f_SCK
Clock frequency
t_CYC
Cycle time
t_LEAD
CS lead time
t_LAG
CS lag time
t_WH
Clock HIGH time
t_WL
Clock LOW time
t_SU
Data setup time
t_H
Data hold time
t_RI (Note 3) Input rise time
t_FI (Note 3) Input fall time
t_CS
CS deselect time
t_WC (Note 4) Write cycle time
DATA OUTPUT TIMING
0
3.3
MHz
300
ns
150
ns
150
ns
130
ns
130
ns
20
ns
20
ns
2
µs
2
µs
100
ns
10
ms
f_SCK
Clock frequency
0
3.3
MHz
t_DIS
Output disable time
150
ns
t_V
Output valid from clock low
130
ns
t_HO
Output hold time
0
ns
t_RO (Note 3) Output rise time
50
ns
t_FO (Note 3) Output fall time
50
ns
NOTES:
3. This parameter is periodically sampled and not 100% tested.
4. t_WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.
15
FN8127.3
June 15, 2006