X5083_06 Datasheet, PDF (2/21 Pages) Intersil Corporation – CPU Supervisor with 8Kbit SPI EEPROM

Typical Application
2.7-5.0V
VCC
X5083
RESET
CS
SCK
SI
SO
WP
VSS
VCC
uC
10K
RESET
SPI
VSS
X5083
Block Diagram
V_CC
CS/WDI
SI
SO
SCK
WP
+
V_TRIP
-
POR AND LOW
VOLTAGE RESET
GENERATION
RESET & WATCHDOG
TIMEBASE
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
RESET
COMMAND
DECODE &
CONTROL
LOGIC
PROTECT LOGIC
STATUS
REGISTER
EEPROM
ARRAY
8KBITS
RESET (X5083)
X5083
STANDARD V_TRIP LEVEL
4.63V (+/-2.5%)
SUFFIX
-4.5A
4.38V (+/-2.5%)
-4.5
2.93V (+/-2.5%)
-2.7A
2.63V (+/-2.5%)
-2.7
See “Ordering Information” on page 3 for
more details
For Custom Settings, call Intersil.
2
FN8127.3
June 15, 2006